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Merge branch 'riscv:master' into master CI #23: Commit a0099b7 pushed by rsnikhil
March 31, 2024 18:54 24m 42s master
master
March 31, 2024 18:54 24m 42s
Merge branch 'riscv:master' into master CI #22: Commit 932469c pushed by rsnikhil
March 25, 2024 13:24 24m 34s master
master
March 25, 2024 13:24 24m 34s
Merge branch 'riscv:master' into master CI #21: Commit 4bee248 pushed by rsnikhil
March 11, 2024 12:57 24m 40s master
master
March 11, 2024 12:57 24m 40s
Old vmem code had much 'cut-and-paste' replication for RV32 (Sv32) and CI #20: Commit 9ccf1d5 pushed by rsnikhil
February 19, 2024 02:53 24m 34s master
master
February 19, 2024 02:53 24m 34s
Add m/senvcfg to CSR name map CI #19: Commit 9602e3a pushed by rsnikhil
February 19, 2024 00:03 23m 50s master
master
February 19, 2024 00:03 23m 50s
Small local modifications to address PR review comments: CI #18: Commit 53a116e pushed by rsnikhil
January 14, 2024 23:26 24m 12s master
master
January 14, 2024 23:26 24m 12s
In vmem code, renamed Level to more descriptive PTW_Level CI #17: Commit 5668f60 pushed by rsnikhil
January 2, 2024 21:52 24m 55s master
master
January 2, 2024 21:52 24m 55s
Tweaks to vmem code to improve type-checking and style CI #16: Commit c3d3bd6 pushed by rsnikhil
January 2, 2024 20:51 23m 47s master
master
January 2, 2024 20:51 23m 47s
Merge branch 'riscv:master' into master CI #15: Commit 29ffe30 pushed by rsnikhil
January 2, 2024 16:26 24m 48s master
master
January 2, 2024 16:26 24m 48s
More updates (mostly stylistic) in response to PR comments CI #14: Commit 1a2e5be pushed by rsnikhil
December 18, 2023 16:15 24m 52s master
master
December 18, 2023 16:15 24m 52s
Merge branch 'riscv:master' into master CI #13: Commit abc9f0d pushed by rsnikhil
December 18, 2023 14:27 24m 29s master
master
December 18, 2023 14:27 24m 29s
Converted all tabs to spaces, per recommended style for sail-riscv CI #12: Commit 1ec8d87 pushed by rsnikhil
December 12, 2023 15:05 24m 33s master
master
December 12, 2023 15:05 24m 33s
Merge branch 'riscv:master' into master CI #11: Commit b6ce2c9 pushed by rsnikhil
December 12, 2023 00:26 24m 36s master
master
December 12, 2023 00:26 24m 36s
Fix a trailing whitespace CI #10: Commit 25f4502 pushed by rsnikhil
December 12, 2023 00:01 24m 24s master
master
December 12, 2023 00:01 24m 24s
In riscv_vmem.sail, recoded 8 LSBs of PTE (D,A,G,U,X,W,R,V) as a Sail… CI #9: Commit 3ec6e19 pushed by rsnikhil
December 11, 2023 23:02 38s master
master
December 11, 2023 23:02 38s
Further tweaks based on recent comments on PR #365 CI #8: Commit 98351d2 pushed by rsnikhil
December 6, 2023 14:49 25m 14s master
master
December 6, 2023 14:49 25m 14s
In riscv_vmem{_tlb}.sail, more style improvements based on comments i… CI #7: Commit ded1c57 pushed by rsnikhil
December 5, 2023 20:14 24m 35s master
master
December 5, 2023 20:14 24m 35s
Formatting tweaks in riscv_vmem.sail and riscv_vmem_tlb.sail CI #6: Commit 62a7e41 pushed by rsnikhil
December 5, 2023 03:31 25m 57s master
master
December 5, 2023 03:31 25m 57s
In riscv_vmem.sail, simplified/cleaned up is_valid_vAddr CI #5: Commit 8b39fca pushed by rsnikhil
December 5, 2023 01:48 27m 23s master
master
December 5, 2023 01:48 27m 23s
Tweak; removed some redundant stuff in SV_Params in riscv_vmem.sail CI #4: Commit 14f4e6e pushed by rsnikhil
December 4, 2023 21:43 29m 24s master
master
December 4, 2023 21:43 29m 24s
Updates (mostly stylistic) based on comments on PR on 91efb546 CI #3: Commit 225b9cf pushed by rsnikhil
December 4, 2023 19:10 25m 56s master
master
December 4, 2023 19:10 25m 56s
CI CI #2: Manually run by rsnikhil
December 1, 2023 20:00 25m 1s master
master
December 1, 2023 20:00 25m 1s
CI CI #1: Manually run by rsnikhil
December 1, 2023 20:00 25m 41s master
master
December 1, 2023 20:00 25m 41s