Skip to content

Commit

Permalink
Rename some interrupt functions
Browse files Browse the repository at this point in the history
) enable_irq -> interrupt_unmask
) disable_irq -> interrupt_mask
) set_pending -> interrupt_pend
) check_irq_pending -> interrupt_is_pending
) set_pending -> interrupt_pend
  • Loading branch information
thejpster committed Sep 1, 2024
1 parent 1aa792e commit 4c95771
Show file tree
Hide file tree
Showing 3 changed files with 24 additions and 23 deletions.
2 changes: 1 addition & 1 deletion rp235x-hal-examples/src/bin/powman_test.rs
Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ fn main() -> ! {
_ = writeln!(&GLOBAL_UART, "AOT time: 0x{:016x}", powman.aot_get_time());

unsafe {
hal::arch::enable_irq(pac::Interrupt::POWMAN_IRQ_TIMER);
hal::arch::interrupt_unmask(pac::Interrupt::POWMAN_IRQ_TIMER);
hal::arch::interrupt_enable();
}

Expand Down
35 changes: 18 additions & 17 deletions rp235x-hal/src/arch.rs
Original file line number Diff line number Diff line change
Expand Up @@ -33,29 +33,29 @@ mod inner {
}

/// Placeholder function to check if an IRQ is pending
pub fn check_irq_pending(irq: rp235x_pac::Interrupt) -> bool {
pub fn interrrupt_is_pending(irq: rp235x_pac::Interrupt) -> bool {
cortex_m::peripheral::NVIC::is_pending(irq)
}

/// Placeholder function to enable an IRQ
/// Enable an RP235x IRQ
///
/// This function is unsafe because it can break mask-based critical sections.
pub unsafe fn enable_irq(irq: rp235x_pac::Interrupt) {
pub unsafe fn interrupt_unmask(irq: rp235x_pac::Interrupt) {
unsafe { cortex_m::peripheral::NVIC::unmask(irq) }
}

/// Placeholder function to disable an IRQ
pub fn disable_irq(irq: rp235x_pac::Interrupt) {
/// Disable an RP235x IRQ
pub fn interrupt_mask(irq: rp235x_pac::Interrupt) {
cortex_m::peripheral::NVIC::mask(irq)
}

/// Placeholder function to check if an IRQ is enabled
pub fn is_irq_enabled(irq: rp235x_pac::Interrupt) -> bool {
/// Check if an RP235x IRQ is enabled
pub fn interrupt_is_enabled(irq: rp235x_pac::Interrupt) -> bool {
cortex_m::peripheral::NVIC::is_enabled(irq)
}

/// Placeholder function to mark an IRQ as pending
pub fn set_pending(irq: rp235x_pac::Interrupt) {
/// Mark an RP235x IRQ as pending
pub fn interrupt_pend(irq: rp235x_pac::Interrupt) {
cortex_m::peripheral::NVIC::pend(irq)
}
}
Expand All @@ -67,8 +67,8 @@ mod inner {

/// Enable interrupts
///
/// Our version is sure to enable Machine External interrupt as well as the
/// global interrupt flag.
/// Enable the Machine External interrupt as well as the global interrupt
/// flag.
#[inline(always)]
pub fn interrupt_enable() {
unsafe {
Expand Down Expand Up @@ -109,7 +109,8 @@ mod inner {
}

pub use crate::xh3irq::{
check_irq_pending, disable_irq, enable_irq, is_irq_enabled, set_pending,
is_enabled as interrupt_is_enabled, is_pending as interrrupt_is_pending,
mask as interrupt_mask, pend as interrupt_pend, unmask as interrupt_unmask,
};

#[no_mangle]
Expand Down Expand Up @@ -512,25 +513,25 @@ mod inner {
pub fn sev() {}

/// Placeholder function to check if an IRQ is pending
pub fn check_irq_pending(irq: rp235x_pac::Interrupt) -> bool {
pub fn interrrupt_is_pending(irq: rp235x_pac::Interrupt) -> bool {
false
}

/// Placeholder function to enable an IRQ
///
/// This function is unsafe because it can break mask-based critical sections.
pub unsafe fn enable_irq(irq: rp235x_pac::Interrupt) {}
pub unsafe fn interrupt_mask(irq: rp235x_pac::Interrupt) {}

/// Placeholder function to disable an IRQ
pub fn disable_irq(irq: rp235x_pac::Interrupt) {}
pub fn interrupt_unmask(irq: rp235x_pac::Interrupt) {}

/// Placeholder function to check if an IRQ is enabled
pub fn is_irq_enabled(irq: rp235x_pac::Interrupt) -> bool {
pub fn interrupt_is_enabled(irq: rp235x_pac::Interrupt) -> bool {
false
}

/// Placeholder function to mark an IRQ as pending
pub fn set_pending(irq: rp235x_pac::Interrupt) {}
pub fn interrupt_pend(irq: rp235x_pac::Interrupt) {}
}

pub use inner::*;
Expand Down
10 changes: 5 additions & 5 deletions rp235x-hal/src/xh3irq.rs
Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ pub const RVCSR_MEINEXT_OFFSET: u32 = 0xbe4;

/// Check if a given interrupt is pending
#[cfg(all(target_arch = "riscv32", target_os = "none"))]
pub fn check_irq_pending(irq: rp235x_pac::Interrupt) -> bool {
pub fn is_pending(irq: rp235x_pac::Interrupt) -> bool {
let (index, bits) = interrupt_to_mask(irq);
let index = index as u32;
let mut csr_rdata: u32;
Expand All @@ -116,7 +116,7 @@ pub fn check_irq_pending(irq: rp235x_pac::Interrupt) -> bool {
///
/// This function is unsafe because it can break mask-based critical sections.
#[cfg(all(target_arch = "riscv32", target_os = "none"))]
pub unsafe fn enable_irq(irq: rp235x_pac::Interrupt) {
pub unsafe fn unmask(irq: rp235x_pac::Interrupt) {
let mask_index = interrupt_to_mask_index(irq);
// Do a RISC-V CSR Set on RVCSR_MEIEA_OFFSET
unsafe {
Expand All @@ -129,7 +129,7 @@ pub unsafe fn enable_irq(irq: rp235x_pac::Interrupt) {

/// Disable an interrupt
#[cfg(all(target_arch = "riscv32", target_os = "none"))]
pub fn disable_irq(irq: rp235x_pac::Interrupt) {
pub fn mask(irq: rp235x_pac::Interrupt) {
let mask_index = interrupt_to_mask_index(irq);
// Do a RISC-V CSR Clear on RVCSR_MEIEA_OFFSET
unsafe {
Expand All @@ -142,7 +142,7 @@ pub fn disable_irq(irq: rp235x_pac::Interrupt) {

/// Check if an interrupt is enabled
#[cfg(all(target_arch = "riscv32", target_os = "none"))]
pub fn is_irq_enabled(irq: rp235x_pac::Interrupt) -> bool {
pub fn is_enabled(irq: rp235x_pac::Interrupt) -> bool {
let (index, bits) = interrupt_to_mask(irq);
let index = index as u32;
let mut csr_rdata: u32;
Expand All @@ -160,7 +160,7 @@ pub fn is_irq_enabled(irq: rp235x_pac::Interrupt) -> bool {

/// Set an interrupt as pending, even if it isn't.
#[cfg(all(target_arch = "riscv32", target_os = "none"))]
pub fn set_pending(irq: rp235x_pac::Interrupt) {
pub fn pend(irq: rp235x_pac::Interrupt) {
let mask_index = interrupt_to_mask_index(irq);
// Do a RISC-V CSR Set on RVCSR_MEIFA_OFFSET
unsafe {
Expand Down

0 comments on commit 4c95771

Please sign in to comment.