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This backend triggers
MachineEnvCall
exceptions to obtain the desired behavior.The
examples/ecall.rs
works following this approach. I still want to make sure that there are no soundness issues before merging this PR. I also use the new approach I'm developing for the RISC-V ecosystem, so it is better to wait until all these changes are published to crates.io.If this approach works, then any RISC-V target will be compatible with
riscv-slic
, regardless of having CLINT or another software interrupt peripheral 😁