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update dependencies
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romancardenas committed Dec 29, 2023
1 parent e6706f7 commit 38700c0
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Showing 2 changed files with 4 additions and 5 deletions.
5 changes: 2 additions & 3 deletions hifive1-test/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,9 @@ edition = "2021"

[dependencies]
riscv-slic = {path = "../riscv-slic", features = ["clint-backend", "unsafe-assume-single-core"]}
e310x = { git = "https://github.com/greenlsi/e310x.git", rev = "f22b4dd"}
hifive1 = { git = "https://github.com/greenlsi/hifive1.git", branch = "rtc", features = ["board-redv"] }
e310x = { git = "https://github.com/greenlsi/e310x.git", branch = "master"}
hifive1 = { git = "https://github.com/romancardenas/hifive1.git", branch = "master", features = ["board-redv"] }
bare-metal = "0.2"
# riscv-rt = "0.11.0"
riscv-rt = {git = "https://github.com/rust-embedded/riscv-rt.git", branch = "master"}
# riscv-rt = {path = "../../../github/riscv-rt", features = ["atomic-emulation-trap"]}
panic-halt = "0.2.0"
4 changes: 2 additions & 2 deletions riscv-slic-macros/src/export/clint.rs
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ pub fn export_quote(input: &CodegenInput) -> TokenStream {
#[inline]
#[no_mangle]
pub unsafe fn __riscv_slic_swi_pend() {
let msip = #pac::CLINT::mswi().msip(#pac::clint::HartId::#hart_id);
let msip = #pac::CLINT::mswi().msip(#pac::HartId::#hart_id);
msip.pend();
}

Expand All @@ -65,7 +65,7 @@ pub fn export_quote(input: &CodegenInput) -> TokenStream {
#[inline]
#[no_mangle]
pub unsafe fn __riscv_slic_swi_unpend() {
let msip = #pac::CLINT::mswi().msip(#pac::clint::HartId::#hart_id);
let msip = #pac::CLINT::mswi().msip(#pac::HartId::#hart_id);
msip.unpend();
}
}
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