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Disable ARM hacks for Capstone 6 #4159

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Jan 27, 2024
Merged

Disable ARM hacks for Capstone 6 #4159

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5 changes: 5 additions & 0 deletions librz/asm/p/asm_arm_cs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,10 @@
#include <capstone/capstone.h>
#include "../arch/arm/asm-arm.h"
#include "../arch/arm/arm_it.h"

#if CS_NEXT_VERSION < 6
#include "./asm_arm_hacks.inc"
#endif

typedef struct arm_cs_context_t {
RzArmITContext it;
Expand Down Expand Up @@ -146,10 +149,12 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
if (!buf) {
goto beach;
}
#if CS_NEXT_VERSION < 6
int haa = hackyArmAsm(a, op, buf, len);
if (haa > 0) {
return haa;
}
#endif

n = cs_disasm(ctx->cd, buf, RZ_MIN(4, len), a->pc, 1, &insn);
if (n < 1 || insn->size < 1) {
Expand Down
18 changes: 9 additions & 9 deletions test/db/analysis/arm64
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Original file line number Diff line number Diff line change
Expand Up @@ -118,10 +118,10 @@ cycles: 0
family: sec
--
address: 0x100007f14
opcode: addg x9, x8, 0x20, 0x0
opcode: addg x9, x8, 0x20, 0
esilcost: 0
disasm: addg x9, x8, 0x20, 0x0
pseudo: asm("addg x9, x8, 0x20, 0x0")
disasm: addg x9, x8, 0x20, 0
pseudo: asm("addg x9, x8, 0x20, 0")
mnemonic: addg
mask: ffffffff
prefix: 0
Expand Down Expand Up @@ -149,10 +149,10 @@ ao@ 8
EOF
EXPECT=<<EOF
address: 0x0
opcode: addg x12, x8, 0x0, 0x2
opcode: addg x12, x8, 0x200, 2
esilcost: 0
disasm: addg x12, x8, 0x0, 0x2
pseudo: asm("addg x12, x8, 0x0, 0x2")
disasm: addg x12, x8, 0x200, 2
pseudo: asm("addg x12, x8, 0x200, 2")
mnemonic: addg
mask: ffffffff
prefix: 0
Expand All @@ -166,10 +166,10 @@ cycles: 0
family: sec
---
address: 0x4
opcode: addg x9, x8, 0x20, 0x0
opcode: addg x9, x8, 0x20, 0
esilcost: 0
disasm: addg x9, x8, 0x20, 0x0
pseudo: asm("addg x9, x8, 0x20, 0x0")
disasm: addg x9, x8, 0x20, 0
pseudo: asm("addg x9, x8, 0x20, 0")
mnemonic: addg
mask: ffffffff
prefix: 0
Expand Down
14 changes: 7 additions & 7 deletions test/db/asm/arm_64
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Original file line number Diff line number Diff line change
Expand Up @@ -326,24 +326,24 @@ a "msr SP_EL0, x3" 034118d5
a "msr sp_el0, x3" 034118d5
a "cbnz w3, 0x1fffd4" a3feff35
a "cbz x3, 0x1fffe8" 43ffffb4
d "addg x0, sp, 0x80, 0x4" e0138891
dE "addg x12, x8, 0x0, 0x2" 91a0090c
d "addg x0, sp, 0x80, 4" e0138891
dE "addg x12, x8, 0x200, 2" 91a0090c
d "subg x0, sp, 0x20, 0xf" e03f82d1
d "irg sp, x0" 1f10df9a
d "irg x13, x3, x7" 6d10c79a
d "subp x13, x7, sp" ed00df9a
d "gmi x13, x3, x7" 6d14c79a
d "subps x13, x3, x7" 6d00c7ba
d "cmpp sp, x13" ff03cdba
d "stg x13, [x3], 0x0" 6d0420d9
d "subps xzr, sp, x13" ff03cdba
d "stg x13, [x3], 0" 6d0420d9
d "stg x13, [x3, 0x10]" 6d1820d9
d "stg x13, [x3, 0x10]!" 6d1c20d9
d "stzgm x12, [x0]" 0c0020d9
d "ldg x13, [x3, 0x10]" 6d1060d9
d "ldg x13, [x3, 0x0]" 6d0060d9
d "ldg x13, [x3]" 6d0060d9
d "stzg x13, [x3], 0x10" 6d1460d9
d "stzg x13, [x3, 0x0]" 6d0860d9
d "stzg x13, [x3, 0x0]!" 6d0c60d9
d "stzg x13, [x3]" 6d0860d9
d "stzg x13, [x3, 0]!" 6d0c60d9
d "st2g sp, [sp], 0x20" ff27a0d9
d "stgm x0, [x1]" 2000a0d9
d "stz2g sp, [sp], 0x50" ff57e0d9
Expand Down
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