[RzIL] IL lifting of SuperH ISA #2518
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DMaroo
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wargio
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DMaroo
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XVilka
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* Link both `sh/assembler.c` and `sh/disassembler.c` with `sh/lookup.c`
* Store the IL context in an `SHILContext` struct and pass it around
to store information to be used outside the lifter
* Remove incorrect comments * Remove unnecessary helper `sh_return_val_if_invalid_gpr`
* Also fix bugs in the corresponding liftings, if any
* Also fix IL liftings for incorrectly implemented shift instructions
* Fix disassmbler/assembler lookup table for incorrectly decoded shift
instructions
* Fix IL lifter for incorrectly implemented branch instructions
* Format according to clang-format
* Now the assembler and dissasembler find the correct instruction from
the lookup table in case of `LDC` (and `STC` as well)
* Banked register instructions are also assembled and disassembled
properly
* Add banked registers in `sh_registers`
* Add tests for `LDC`
* Fix `sh_il_set_status_reg` to use `LSB` leading to concise IL dumps
* Add a member in `SHILContext`, `use_banked` to decide whether to use
banked registers or not in case privileged mode. Very helpful in
case of `LDC`, `LDC.L`, `STC`, `STC.L`
* Fix `sh_il_get_status_reg` to use remove double casting and use
appropriate bits for `SH_SR_I`
* Fix incorrectly implemented system control IL lifters
wargio
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wingdeans
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Aug 3, 2022
* Add an assembler for the SuperH ISA * Rewrite GPL GNU disassembler code
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Detailed description
Lifting SuperH ISA to RzIL.
Architecture reference: https://www.st.com/resource/en/user_manual/cd00147165-sh-4-32-bit-cpu-core-architecture-stmicroelectronics.pdf
I have also implemented a disassembler and assembler for SuperH.
Test plan
I have added one IL test for every instruction which was implemented. It is yet to be tested against
rz-tracetest, but the asm tests are passing.Closing issues
Tracking issue: #2080
Unimplemented instructions
LDTLBOCBIOCBPOCBWBPREFTRAPAForLDCandSTC, the instruction involving banked registers as the operands is unimplemented (more like incorrectly implemented) in the IL