Fix reachable Capstone assert. (#4571)

ESIL requested a register name with a non-register value.
rizinorg · Jul 16, 2024 · e878181 · e878181
1 parent d004e84
commit e878181
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diff --git a/librz/arch/isa/arm/arm_esil32.c b/librz/arch/isa/arm/arm_esil32.c
@@ -852,6 +852,10 @@ r6,r5,r4,3,sp,[*],12,sp,+=
 		// TODO: esil for MRS
 		break;
 	case ARM_INS_MSR:
+		if (insn->detail->arm.operands[0].type != ARM_OP_REG) {
+			// New sysop operands added in Capstone v6 are not supported in ESIL.
+			break;
+		}
 #if CS_NEXT_VERSION >= 6
 		msr_flags = insn->detail->arm.operands[0].sysop.msr_mask;
 #else

diff --git a/test/db/esil/arm_32 b/test/db/esil/arm_32
@@ -2970,3 +2970,19 @@ d0 = 0x01c00df0fecadec0
 d1 = 0xaaaaaaaaaaaaaaaa
 EOF
 RUN
+
+NAME=reachable capstone assert
+FILE=malloc://0x100
+CMDS=<<EOF
+e esil.verbose=2
+e asm.arch=arm
+e asm.bits=32
+wx fbfd21b3 # msrlt cpsr_c, #0x3ec0
+pi 1
+pie 1
+EOF
+EXPECT=<<EOF
+msrlt cpsr_c, 0x3ec0
+0x00000000 nf,vf,^,?{,,}
+EOF
+RUN