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fix xtensa stack inc and ret
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@imbillow
imbillow committed Nov 5, 2024
1 parent c31e2d4 commit 96cbff4
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Showing 3 changed files with 58 additions and 49 deletions.
4 changes: 2 additions & 2 deletions librz/arch/isa/xtensa/xtensa.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,9 +44,9 @@ static inline int32_t xtensa_op_l32r(cs_insn *insn, unsigned int index) {
return op->imm;
}

#define REG(I) cs_reg_name(ctx->handle, I)
#define MEM(I) xtensa_op_mem(ctx->insn, I)
#define REGO(I) REG(xtensa_op_reg(ctx->insn, I))
#define REGI(I) xtensa_op_reg(ctx->insn, I)
#define REGN(I) cs_reg_name(ctx->handle, (xtensa_op_reg(ctx->insn, I)))
#define IMM(I) xtensa_op_imm(ctx->insn, I)
#define L32R(I) xtensa_op_l32r(ctx->insn, I)
#define INSN_SIZE (ctx->insn->size)
Expand Down
88 changes: 44 additions & 44 deletions librz/arch/isa/xtensa/xtensa_esil.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ static void esil_load_imm(XtensaContext *ctx, RzAnalysisOp *op) {
// offset
MEM(1)->disp,
// address
REG(MEM(1)->base),
cs_reg_name(ctx->handle, MEM(1)->base),
// size
data_size);

Expand All @@ -91,7 +91,7 @@ static void esil_load_imm(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"=",
// data
REGO(0));
REGN(0));
}

static void esil_load_relative(XtensaContext *ctx, RzAnalysisOp *op) {
Expand All @@ -112,21 +112,21 @@ static void esil_load_relative(XtensaContext *ctx, RzAnalysisOp *op) {
// offset
L32R(1),
// data
REGO(0));
REGN(0));
}

static void esil_add_imm(XtensaContext *ctx, RzAnalysisOp *op) {
// example: addi a3, a4, 0x01
// a4,0x01,+,a3,=

rz_strbuf_appendf(&op->esil, "%s" CM, REGO(1));
rz_strbuf_appendf(&op->esil, "%s" CM, REGN(1));
esil_push_signed_imm(&op->esil, IMM(2));
rz_strbuf_appendf(
&op->esil,
"+" CM
"%s" CM
"=",
REGO(0));
REGN(0));
}

static void esil_store_imm(XtensaContext *ctx, RzAnalysisOp *op) { // example: s32i a2, a1, 0x10
Expand All @@ -149,9 +149,9 @@ static void esil_store_imm(XtensaContext *ctx, RzAnalysisOp *op) { // example: s
"+" CM
"=[%d]",
// data
REGO(0),
REGN(0),
// address
REG(MEM(1)->base),
cs_reg_name(ctx->handle, MEM(1)->base),
// offset
MEM(1)->disp,
// size
Expand All @@ -164,7 +164,7 @@ static void esil_move_imm(XtensaContext *ctx, RzAnalysisOp *op) {
&op->esil,
"%s" CM
"=",
REGO(0));
REGN(0));
}

static void esil_move(XtensaContext *ctx, RzAnalysisOp *op) {
Expand All @@ -173,8 +173,8 @@ static void esil_move(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"%s" CM
"=",
REGO(1),
REGO(0));
REGN(1),
REGN(0));
}

static void esil_move_conditional(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down Expand Up @@ -215,10 +215,10 @@ static void esil_move_conditional(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"=" CM
"}",
REGO(2),
REGN(2),
compare_op,
REGO(1),
REGO(0));
REGN(1),
REGN(0));
}

static ut8 add_sub_shift(XtensaContext *ctx) {
Expand Down Expand Up @@ -260,11 +260,11 @@ static void esil_add_sub(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"%s" CM
"=",
REGO(2),
REGN(2),
add_sub_shift(ctx),
REGO(1),
REGN(1),
(add_sub_is_add(ctx) ? "+" : "-"),
REGO(0));
REGN(0));
}

static void esil_branch_compare_imm(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down Expand Up @@ -302,7 +302,7 @@ static void esil_branch_compare_imm(XtensaContext *ctx, RzAnalysisOp *op) {
&op->esil,
"%s" CM,
// data reg
REGO(0));
REGN(0));

esil_push_signed_imm(&op->esil, IMM(1));

Expand Down Expand Up @@ -351,8 +351,8 @@ static void esil_branch_compare(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"%s" CM
"?{" CM,
REGO(1),
REGO(0),
REGN(1),
REGN(0),
compare_op);

esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
Expand Down Expand Up @@ -396,7 +396,7 @@ static void esil_branch_compare_single(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"%s" CM
"?{" CM,
REGO(0),
REGN(0),
compare_op);

esil_push_signed_imm(&op->esil, IMM(1) - INSN_SIZE);
Expand Down Expand Up @@ -426,7 +426,7 @@ static void esil_branch_check_mask(XtensaContext *ctx, RzAnalysisOp *op) {
compare_val,
sizeof(compare_val),
"%s",
REGO(1));
REGN(1));
break;
}

Expand All @@ -450,9 +450,9 @@ static void esil_branch_check_mask(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"%s" CM
"?{" CM,
REGO(0),
REGO(1),
REGO(1),
REGN(0),
REGN(1),
REGN(1),
compare_op);

esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
Expand Down Expand Up @@ -484,10 +484,10 @@ static void esil_bitwise_op(XtensaContext *ctx, RzAnalysisOp *op) {
"%c" CM
"%s" CM
"=",
REGO(1),
REGO(2),
REGN(1),
REGN(2),
bop,
REGO(0));
REGN(0));
}

static void esil_branch_check_bit_imm(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down Expand Up @@ -517,7 +517,7 @@ static void esil_branch_check_bit_imm(XtensaContext *ctx, RzAnalysisOp *op) {
"0" CM
"%s" CM
"?{" CM,
REGO(0),
REGN(0),
IMM(1),
cmp_op);

Expand Down Expand Up @@ -562,8 +562,8 @@ static void esil_branch_check_bit(XtensaContext *ctx, RzAnalysisOp *op) {
"0" CM
"%s" CM
"?{" CM,
REGO(1),
REGO(0),
REGN(1),
REGN(0),
cmp_op);

esil_push_signed_imm(&op->esil, IMM(2) - INSN_SIZE);
Expand Down Expand Up @@ -596,24 +596,24 @@ static void esil_abs_neg(XtensaContext *ctx, RzAnalysisOp *op) {
"?{" CM
"%s" CM
"}" CM,
REGO(0),
REGO(0),
REGO(0),
REGO(0));
REGN(0),
REGN(0),
REGN(0),
REGN(0));
} else {
rz_strbuf_appendf(
&op->esil,
"0" CM
"%s" CM
"-" CM,
REGO(0));
REGN(0));
}

rz_strbuf_appendf(
&op->esil,
"%s" CM
"=" CM,
REGO(1));
REGN(1));
}

static void esil_call(XtensaContext *ctx, RzAnalysisOp *op) {
Expand All @@ -635,7 +635,7 @@ static void esil_callx(XtensaContext *ctx, RzAnalysisOp *op) {
rz_strbuf_appendf(
&op->esil,
"%s" CM "0" CM "+" CM,
REGO(0));
REGN(0));

if (callx) {
rz_strbuf_append(
Expand All @@ -654,7 +654,7 @@ static void esil_set_shift_amount(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"sar" CM
"=",
REGO(0));
REGN(0));
}

static void esil_set_shift_amount_imm(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down Expand Up @@ -684,9 +684,9 @@ static void esil_shift_logic_imm(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"=",
IMM(2),
REGO(1),
REGN(1),
shift_op,
REGO(0));
REGN(0));
}

static void esil_shift_logic_sar(XtensaContext *ctx, RzAnalysisOp *op) {
Expand All @@ -705,9 +705,9 @@ static void esil_shift_logic_sar(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"%s" CM
"=",
REGO(1),
REGN(1),
shift_op,
REGO(0));
REGN(0));
}

static void esil_extract_unsigned(XtensaContext *ctx, RzAnalysisOp *op) {
Expand All @@ -721,9 +721,9 @@ static void esil_extract_unsigned(XtensaContext *ctx, RzAnalysisOp *op) {
"%s" CM
"=",
IMM(2),
REGO(1),
REGN(1),
(1 << IMM(3)) - 1,
REGO(0));
REGN(0));
}

void xtensa_analyze_op_esil(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down
15 changes: 12 additions & 3 deletions librz/arch/p/analysis/analysis_xtensa_cs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -115,6 +115,7 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
case XTENSA_INS_ADDX4: /* addx4 */
case XTENSA_INS_ADDX8: /* addx8 */
case XTENSA_INS_ADD_N:
case XTENSA_INS_ADD_S:
op->type = RZ_ANALYSIS_OP_TYPE_ADD;
break;
case XTENSA_INS_SUB: /* sub */
Expand All @@ -139,11 +140,19 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
op->type = RZ_ANALYSIS_OP_TYPE_STORE;
break;
case XTENSA_INS_ADDI: /* addi */
case XTENSA_INS_ADDI_N:
case XTENSA_INS_ADD_S:
case XTENSA_INS_ADDI_N: {
op->type = RZ_ANALYSIS_OP_TYPE_ADD;
// a1 = stack
if (REGI(0) == XTENSA_REG_SP && REGI(1) == XTENSA_REG_SP) {
op->val = IMM(2);
op->stackptr = -IMM(2);
op->stackop = RZ_ANALYSIS_STACK_INC;
}
break;
}
case XTENSA_INS_RET: /* ret */
case XTENSA_INS_RET_N:
case XTENSA_INS_RETW_N:
op->eob = true;
op->type = RZ_ANALYSIS_OP_TYPE_RET;
break;
Expand Down Expand Up @@ -208,7 +217,7 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
break;
case XTENSA_INS_CALLX0: /* callx0 */
op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
op->reg = REGO(0);
op->reg = REGN(0);
break;
case XTENSA_INS_MOVEQZ: /* moveqz */
case XTENSA_INS_MOVNEZ: /* movnez */
Expand Down

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