Remove NIOS-II architecture (#4457)

rizinorg · Apr 24, 2024 · 9526b6c · 9526b6c
1 parent c2e0348
commit 9526b6c
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Showing 8 changed files with 1 addition and 1,541 deletions.
diff --git a/librz/arch/isa_gnu/common_gnu/opcode/nios2.h b/librz/arch/isa_gnu/common_gnu/opcode/nios2.h
diff --git a/librz/arch/isa_gnu/nios/nios2-dis.c b/librz/arch/isa_gnu/nios/nios2-dis.c
diff --git a/librz/arch/isa_gnu/nios/nios2-opc.c b/librz/arch/isa_gnu/nios/nios2-opc.c
diff --git a/librz/arch/meson.build b/librz/arch/meson.build
@@ -326,7 +326,6 @@ if get_option('use_gpl')
     'hppa_gnu',
     'lanai_gnu',
     'mips_gnu',
-    'nios2_gnu',
     'riscv_gnu',
     'sparc_gnu',
     'vax_gnu',
@@ -341,7 +340,6 @@ if get_option('use_gpl')
     'p_gnu/arch_hppa.c',
     'p_gnu/arch_lanai.c',
     'p_gnu/arch_mips.c',
-    'p_gnu/arch_nios2.c',
     'p_gnu/arch_riscv.c',
     'p_gnu/arch_sparc.c',
     'p_gnu/arch_vax.c',
@@ -363,8 +361,6 @@ if get_option('use_gpl')
     'isa_gnu/mips/mips-dis.c',
     'isa_gnu/mips/mips-opc.c',
     'isa_gnu/mips/mips16-opc.c',
-    'isa_gnu/nios/nios2-dis.c',
-    'isa_gnu/nios/nios2-opc.c',
     # 'isa_gnu/riscv/riscv-opc.c',
     # 'isa_gnu/riscv/riscv.c',
     'isa_gnu/sparc/sparc-dis.c',

diff --git a/librz/arch/p_gnu/analysis/analysis_nios2_gnu.c b/librz/arch/p_gnu/analysis/analysis_nios2_gnu.c
diff --git a/librz/arch/p_gnu/arch_nios2.c b/librz/arch/p_gnu/arch_nios2.c
diff --git a/librz/arch/p_gnu/asm/asm_nios2_gnu.c b/librz/arch/p_gnu/asm/asm_nios2_gnu.c
diff --git a/test/db/cmd/cmd_list b/test/db/cmd/cmd_list
@@ -442,7 +442,6 @@ _dA__ 32         cris        GPL3    Axis Communications 32-bit embedded process
 _d___ 32         hppa        GPL3    HP PA-RISC
 _d___ 32         lanai       GPL3    LANAI
 adAe_ 32 64      mips.gnu    GPL3    MIPS CPU
-_dA__ 32         nios2       GPL3    NIOS II Embedded Processor
 _dAe_ 32 64      riscv       GPL3    RISC-V
 _dA__ 32 64      sparc.gnu   GPL3    Scalable Processor Architecture
 _dA__ 8 32       vax         GPL3    VAX
@@ -516,7 +515,6 @@ cris
 hppa
 lanai
 mips.gnu
-nios2
 riscv
 sparc.gnu
 vax
@@ -529,7 +527,7 @@ NAME=Print the asm/analysis plugins in JSON
 FILE==
 CMDS=Laj
 EXPECT=<<EOF
-["6502":{"bits":"8 16 ","license":"LGPL3","description":"6502/NES/C64/Tamagotchi/T-1000 CPU","features":"_d"},"8051":{"bits":"8 ","license":"PD","description":"8051 Intel CPU","features":"ad"},"amd29k":{"bits":"32 ","license":"LGPL3","description":"AMD 29k RISC CPU","features":"_d"},"arm.as":{"bits":"16 32 64","license":"LGPL3","description":"as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)","features":"a_"},"arm":{"bits":"16 32 64","license":"BSD","description":"Capstone ARM disassembler","features":"ad"},"avr":{"bits":"8 16 ","license":"LGPL3","description":"AVR Atmel","features":"ad"},"bf":{"bits":"16 32 64","license":"LGPL3","description":"Brainfuck","features":"ad"},"chip8":{"bits":"32 ","license":"LGPL3","description":"Chip8 disassembler","features":"_d"},"cil":{"bits":"16 32 64","license":"LGPL3","description":".NET Common Intermediate Language","features":"_d"},"cr16":{"bits":"16 ","license":"LGPL3","description":"cr16 disassembly plugin","features":"_d"},"dalvik":{"bits":"32 64","license":"LGPL3","description":"AndroidVM Dalvik","features":"ad"},"dcpu16":{"bits":"16 ","license":"PD","description":"Mojang's DCPU-16","features":"ad"},"ebc":{"bits":"32 64","license":"LGPL3","description":"EFI Bytecode","features":"_d"},"gb":{"bits":"16 ","license":"LGPL3","description":"GameBoy(TM) (z80-like)","features":"ad"},"h8300":{"bits":"16 ","license":"LGPL3","description":"H8/300 disassembly plugin","features":"_d"},"hexagon":{"bits":"32 ","license":"LGPL3","description":"Qualcomm Hexagon (QDSP6) V6","features":"_d"},"i4004":{"bits":"4 ","license":"LGPL3","description":"Intel 4004 microprocessor","features":"_d"},"i8080":{"bits":"8 ","license":"BSD","description":"Intel 8080 CPU","features":"_d"},"java":{"bits":"32 ","license":"LGPL-3","description":"Java bytecode disassembler","features":"ad"},"lh5801":{"bits":"8 ","license":"LGPL3","description":"SHARP LH5801 disassembler","features":"_d"},"lm32":{"bits":"32 ","license":"BSD","description":"disassembly plugin for Lattice Micro 32 ISA","features":"_d"},"luac":{"bits":"8 ","license":"LGPL3","description":"luac disassemble plugin","features":"ad"},"m680x":{"bits":"8 32 ","license":"BSD","description":"Capstone M680X Disassembler","features":"_d"},"m68k":{"bits":"32 ","license":"BSD","description":"Capstone M68K disassembler","features":"_d"},"malbolge":{"bits":"32 ","license":"LGPL3","description":"Malbolge Ternary VM","features":"_d"},"mcore":{"bits":"32 ","license":"LGPL3","description":"Motorola MCORE disassembler","features":"_d"},"mcs96":{"bits":"16 ","license":"LGPL3","description":"condrets car","features":"_d"},"mips":{"bits":"16 32 64","license":"BSD","description":"Capstone MIPS disassembler","features":"ad"},"msp430":{"bits":"16 ","license":"LGPL3","description":"msp430 disassembly plugin","features":"_d"},"null":{"bits":"16 32 64","license":"MIT","description":"no disassemble","features":"ad"},"or1k":{"bits":"32 ","license":"LGPL3","description":"OpenRISC 1000","features":"_d"},"pic":{"bits":"8 ","license":"LGPL3","description":"PIC disassembler","features":"_d"},"ppc.as":{"bits":"32 64","license":"LGPL3","description":"as PPC Assembler (use RZ_PPC_AS environment)","features":"a_"},"ppc":{"bits":"32 64","license":"BSD","description":"Capstone PowerPC disassembler","features":"_d"},"propeller":{"bits":"32 ","license":"LGPL3","description":"propeller disassembly plugin","features":"_d"},"pyc":{"bits":"8 16 ","license":"LGPL3","description":"PYC disassemble plugin","features":"_d"},"rl78":{"bits":"32 ","license":"LGPL3","description":"Renesas RL78 disassembler","features":"ad"},"rsp":{"bits":"32 ","license":"LGPL3","description":"Reality Signal Processor","features":"_d"},"rx":{"bits":"32 ","license":"LGPL3","description":"Renesas RX Family disassembler","features":"_d"},"sh":{"bits":"32 ","license":"LGPL3","description":"SuperH-4 CPU","features":"ad"},"snes":{"bits":"8 16 ","license":"LGPL3","description":"SuperNES CPU","features":"_d"},"sparc":{"bits":"32 64","license":"BSD","description":"Capstone SPARC disassembler","features":"_d"},"spc700":{"bits":"16 ","license":"LGPL3","description":"spc700, snes' sound-chip","features":"_d"},"sysz":{"bits":"32 64","license":"BSD","description":"SystemZ CPU disassembler","features":"_d"},"tms320":{"bits":"32 ","license":"LGPL3","description":"TMS320 DSP family (c54x,c55x,c55x+,c64x)","features":"_d"},"v810":{"bits":"32 ","license":"LGPL3","description":"v810 disassembly plugin","features":"_d"},"v850":{"bits":"32 ","license":"LGPL3","description":"v850 disassembly plugin","features":"_d"},"wasm":{"bits":"32 ","license":"MIT","description":"WebAssembly","features":"ad"},"x86.as":{"bits":"16 32 64","license":"LGPL3","description":"Intel X86 GNU Assembler (Use RZ_X86_AS env)","features":"a_"},"x86":{"bits":"16 32 64","license":"BSD","description":"Capstone X86 disassembler","features":"_d"},"x86.nasm":{"bits":"16 32 64","license":"LGPL3","description":"X86 nasm assembler","features":"a_"},"x86.nz":{"bits":"16 32 64","license":"LGPL3","description":"x86 handmade assembler","features":"a_"},"xap":{"bits":"16 ","license":"PD","description":"XAP4 RISC (CSR)","features":"_d"},"xcore":{"bits":"32 ","license":"BSD","description":"Capstone XCore disassembler","features":"_d"},"riscv.cs":{"bits":"32 64","license":"BSD","description":"Capstone RISCV disassembler","features":"_d"},"tricore":{"bits":"32 ","license":"BSD","description":"Siemens TriCore CPU","features":"_d"},"arc":{"bits":"16 32 ","license":"GPL3","description":"Argonaut RISC Core","features":"_d"},"cris":{"bits":"32 ","license":"GPL3","description":"Axis Communications 32-bit embedded processor","features":"_d"},"hppa":{"bits":"32 ","license":"GPL3","description":"HP PA-RISC","features":"_d"},"lanai":{"bits":"32 ","license":"GPL3","description":"LANAI","features":"_d"},"mips.gnu":{"bits":"32 64","license":"GPL3","description":"MIPS CPU","features":"ad"},"nios2":{"bits":"32 ","license":"GPL3","description":"NIOS II Embedded Processor","features":"_d"},"riscv":{"bits":"32 64","license":"GPL3","description":"RISC-V","features":"_d"},"sparc.gnu":{"bits":"32 64","license":"GPL3","description":"Scalable Processor Architecture","features":"_d"},"vax":{"bits":"8 32 ","license":"GPL3","description":"VAX","features":"_d"},"xtensa":{"bits":"32 ","license":"GPL3","description":"XTensa CPU","features":"_d"},"z80":{"bits":"8 ","license":"GPL3","description":"Zilog Z80","features":"ad"}]
+["6502":{"bits":"8 16 ","license":"LGPL3","description":"6502/NES/C64/Tamagotchi/T-1000 CPU","features":"_d"},"8051":{"bits":"8 ","license":"PD","description":"8051 Intel CPU","features":"ad"},"amd29k":{"bits":"32 ","license":"LGPL3","description":"AMD 29k RISC CPU","features":"_d"},"arm.as":{"bits":"16 32 64","license":"LGPL3","description":"as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)","features":"a_"},"arm":{"bits":"16 32 64","license":"BSD","description":"Capstone ARM disassembler","features":"ad"},"avr":{"bits":"8 16 ","license":"LGPL3","description":"AVR Atmel","features":"ad"},"bf":{"bits":"16 32 64","license":"LGPL3","description":"Brainfuck","features":"ad"},"chip8":{"bits":"32 ","license":"LGPL3","description":"Chip8 disassembler","features":"_d"},"cil":{"bits":"16 32 64","license":"LGPL3","description":".NET Common Intermediate Language","features":"_d"},"cr16":{"bits":"16 ","license":"LGPL3","description":"cr16 disassembly plugin","features":"_d"},"dalvik":{"bits":"32 64","license":"LGPL3","description":"AndroidVM Dalvik","features":"ad"},"dcpu16":{"bits":"16 ","license":"PD","description":"Mojang's DCPU-16","features":"ad"},"ebc":{"bits":"32 64","license":"LGPL3","description":"EFI Bytecode","features":"_d"},"gb":{"bits":"16 ","license":"LGPL3","description":"GameBoy(TM) (z80-like)","features":"ad"},"h8300":{"bits":"16 ","license":"LGPL3","description":"H8/300 disassembly plugin","features":"_d"},"hexagon":{"bits":"32 ","license":"LGPL3","description":"Qualcomm Hexagon (QDSP6) V6","features":"_d"},"i4004":{"bits":"4 ","license":"LGPL3","description":"Intel 4004 microprocessor","features":"_d"},"i8080":{"bits":"8 ","license":"BSD","description":"Intel 8080 CPU","features":"_d"},"java":{"bits":"32 ","license":"LGPL-3","description":"Java bytecode disassembler","features":"ad"},"lh5801":{"bits":"8 ","license":"LGPL3","description":"SHARP LH5801 disassembler","features":"_d"},"lm32":{"bits":"32 ","license":"BSD","description":"disassembly plugin for Lattice Micro 32 ISA","features":"_d"},"luac":{"bits":"8 ","license":"LGPL3","description":"luac disassemble plugin","features":"ad"},"m680x":{"bits":"8 32 ","license":"BSD","description":"Capstone M680X Disassembler","features":"_d"},"m68k":{"bits":"32 ","license":"BSD","description":"Capstone M68K disassembler","features":"_d"},"malbolge":{"bits":"32 ","license":"LGPL3","description":"Malbolge Ternary VM","features":"_d"},"mcore":{"bits":"32 ","license":"LGPL3","description":"Motorola MCORE disassembler","features":"_d"},"mcs96":{"bits":"16 ","license":"LGPL3","description":"condrets car","features":"_d"},"mips":{"bits":"16 32 64","license":"BSD","description":"Capstone MIPS disassembler","features":"ad"},"msp430":{"bits":"16 ","license":"LGPL3","description":"msp430 disassembly plugin","features":"_d"},"null":{"bits":"16 32 64","license":"MIT","description":"no disassemble","features":"ad"},"or1k":{"bits":"32 ","license":"LGPL3","description":"OpenRISC 1000","features":"_d"},"pic":{"bits":"8 ","license":"LGPL3","description":"PIC disassembler","features":"_d"},"ppc.as":{"bits":"32 64","license":"LGPL3","description":"as PPC Assembler (use RZ_PPC_AS environment)","features":"a_"},"ppc":{"bits":"32 64","license":"BSD","description":"Capstone PowerPC disassembler","features":"_d"},"propeller":{"bits":"32 ","license":"LGPL3","description":"propeller disassembly plugin","features":"_d"},"pyc":{"bits":"8 16 ","license":"LGPL3","description":"PYC disassemble plugin","features":"_d"},"rl78":{"bits":"32 ","license":"LGPL3","description":"Renesas RL78 disassembler","features":"ad"},"rsp":{"bits":"32 ","license":"LGPL3","description":"Reality Signal Processor","features":"_d"},"rx":{"bits":"32 ","license":"LGPL3","description":"Renesas RX Family disassembler","features":"_d"},"sh":{"bits":"32 ","license":"LGPL3","description":"SuperH-4 CPU","features":"ad"},"snes":{"bits":"8 16 ","license":"LGPL3","description":"SuperNES CPU","features":"_d"},"sparc":{"bits":"32 64","license":"BSD","description":"Capstone SPARC disassembler","features":"_d"},"spc700":{"bits":"16 ","license":"LGPL3","description":"spc700, snes' sound-chip","features":"_d"},"sysz":{"bits":"32 64","license":"BSD","description":"SystemZ CPU disassembler","features":"_d"},"tms320":{"bits":"32 ","license":"LGPL3","description":"TMS320 DSP family (c54x,c55x,c55x+,c64x)","features":"_d"},"v810":{"bits":"32 ","license":"LGPL3","description":"v810 disassembly plugin","features":"_d"},"v850":{"bits":"32 ","license":"LGPL3","description":"v850 disassembly plugin","features":"_d"},"wasm":{"bits":"32 ","license":"MIT","description":"WebAssembly","features":"ad"},"x86.as":{"bits":"16 32 64","license":"LGPL3","description":"Intel X86 GNU Assembler (Use RZ_X86_AS env)","features":"a_"},"x86":{"bits":"16 32 64","license":"BSD","description":"Capstone X86 disassembler","features":"_d"},"x86.nasm":{"bits":"16 32 64","license":"LGPL3","description":"X86 nasm assembler","features":"a_"},"x86.nz":{"bits":"16 32 64","license":"LGPL3","description":"x86 handmade assembler","features":"a_"},"xap":{"bits":"16 ","license":"PD","description":"XAP4 RISC (CSR)","features":"_d"},"xcore":{"bits":"32 ","license":"BSD","description":"Capstone XCore disassembler","features":"_d"},"riscv.cs":{"bits":"32 64","license":"BSD","description":"Capstone RISCV disassembler","features":"_d"},"tricore":{"bits":"32 ","license":"BSD","description":"Siemens TriCore CPU","features":"_d"},"arc":{"bits":"16 32 ","license":"GPL3","description":"Argonaut RISC Core","features":"_d"},"cris":{"bits":"32 ","license":"GPL3","description":"Axis Communications 32-bit embedded processor","features":"_d"},"hppa":{"bits":"32 ","license":"GPL3","description":"HP PA-RISC","features":"_d"},"lanai":{"bits":"32 ","license":"GPL3","description":"LANAI","features":"_d"},"mips.gnu":{"bits":"32 64","license":"GPL3","description":"MIPS CPU","features":"ad"},"riscv":{"bits":"32 64","license":"GPL3","description":"RISC-V","features":"_d"},"sparc.gnu":{"bits":"32 64","license":"GPL3","description":"Scalable Processor Architecture","features":"_d"},"vax":{"bits":"8 32 ","license":"GPL3","description":"VAX","features":"_d"},"xtensa":{"bits":"32 ","license":"GPL3","description":"XTensa CPU","features":"_d"},"z80":{"bits":"8 ","license":"GPL3","description":"Zilog Z80","features":"ad"}]
 EOF
 RUN