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PIC: fix pic18 asm
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imbillow committed Apr 27, 2024
1 parent fe4eab3 commit 523fcdb
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Showing 3 changed files with 329 additions and 157 deletions.
117 changes: 1 addition & 116 deletions librz/arch/isa/pic/pic18_il.inc
Original file line number Diff line number Diff line change
Expand Up @@ -3,121 +3,6 @@

#include <rz_il.h>

static const char *pic18_regnames[] = {
"pcl",
"pclath",
"pclatu",
"bsr",
"tos",
"tosl",
"tosh",
"tosu",
"indf0",
"fsr0",
"fsr0l",
"fsr0h",
"indf1",
"fsr1",
"fsr1l",
"fsr1h",
"indf2",
"fsr2",
"frs2l",
"fsr2h",
"tblptr",
"tblptrl",
"tblptrh",
"tblptru",
"rcon",
"memcon",
"intcon",
"intcon2",
"intcon3",
"pie1",
"porta",
"trisa",
"portb",
"tisb",
"latb",
"portc",
"trisc",
"latc",
"portd",
"trisd",
"latd",
"pspcon",
"porte",
"trise",
"late",
"t0con",
"t1con",
"t2con",
"tmr1h",
"tmr0h",
"tmr1l",
"tmr2",
"pr2",
"ccpr1h",
"postinc2",
"ccpr1l",
"postdec2",
"ccp1con",
"preinc2",
"ccpr2h",
"plusw2",
"ccpr2l",
"ccp2con",
"status",
"c .",
"dc .",
"z .",
"ov .",
"n .",
"prod",
"prodl",
"prodh",
"osccon",
"tmr3h",
"lvdcon",
"tmr3l",
"wdtcon",
"t3con",
"spbrg",
"postinc0",
"rcreg",
"postdec0",
"txreg",
"preinc0",
"txsta",
"plusw0",
"rcsta",
"sspbuf",
"wreg",
"sspadd",
"sspstat",
"postinc1",
"sspcon1",
"postdec1",
"sspcon2",
"preinc1",
"adresh",
"plusw1",
"adresl",
"adcon0",
"stkptr",
"tblat",
"_sram",
"_stack"
};

static const char *pic18_regname(size_t index) {
if (index >= RZ_ARRAY_SIZE(pic18_regnames)) {
rz_warn_if_reached();
return NULL;
}
return pic18_regnames[index];
}

#define K (op->k)
#define D (op->d)
#define F (op->f)
Expand Down Expand Up @@ -510,6 +395,6 @@ static RzILOpEffect *pic18_il(Pic18Op *op) {
static RzAnalysisILConfig *pic18_il_config(
RZ_NONNULL RzAnalysis *analysis) {
RzAnalysisILConfig *cfg = rz_analysis_il_config_new(32, false, 16);
cfg->reg_bindings = pic18_regnames;
cfg->reg_bindings = pic18_reg_bindings();
return cfg;
}
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