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[skip ci]Add rh850 System Registers
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@imbillow
imbillow committed Jan 17, 2024
1 parent da0ffb2 commit 37d452c
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Showing 2 changed files with 124 additions and 47 deletions.
164 changes: 121 additions & 43 deletions librz/analysis/arch/v850/v850_il.c
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Original file line number Diff line number Diff line change
Expand Up @@ -116,42 +116,6 @@ static const char *GR[] = {
/*PC*/
};

static const char *SR[] = {
"EIPC",
"EIPSW",
"FEPC",
"FEPSW",
"ECR",
"PSW", // 5
"RES6",
"RES7",
"RES8",
"RES9",
"RES10",
"RES11",
"RES12",
"RES6",
"RES13",
"RES14",
"RES15",
"RES16",
"RES17",
"RES18",
"RES19",
"RES20",
"RES21",
"RES22",
"RES23",
"RES24",
"RES25",
"RES26",
"RES27",
"RES28",
"RES29",
"RES30",
"RES31",
};

static const char *GR_get(ut8 i) {
if (i >= RZ_ARRAY_SIZE(GR)) {
rz_warn_if_reached();
Expand All @@ -160,12 +124,126 @@ static const char *GR_get(ut8 i) {
return GR[i];
}

static const char *SR_get(ut8 i) {
if (i >= RZ_ARRAY_SIZE(SR)) {
rz_warn_if_reached();
return NULL;
static const char *SR_get(ut8 regID, ut8 selID) {
if (selID == 0) {
switch (regID) {
case 0: return "EIPC";
case 1: return "EIPSW";
case 2: return "FEPC";
case 3: return "FEPSW";
case 4: return "ECR";
case 5: return "PSW";
case 6: return "FPSR";
case 7: return "FPEPC";
case 8: return "FPST";
case 9: return "FPCC";
case 10: return "FPCFG";
case 11: return "FPEC";
case 13: return "EIIC";
case 14: return "FEIC";
case 16: return "CTPC";
case 17: return "CTPSW";
case 20: return "CTBP";
case 28: return "EIWR";
case 29: return "FEWR";
case 31: return "BSEL";
default: break;
}
} else if (selID == 1) {
switch (regID) {
case 0: return "MCFG0";
case 2: return "RBASE";
case 3: return "EBASE";
case 4: return "INTBP";
case 5: return "MCTL";
case 6: return "PID";
case 7: return "FPIPR";
case 11: return "SCCFG";
case 12: return "SCBP";
default: break;
}
} else if (selID == 2) {
switch (regID) {
case 0: return "HTCFG0";
case 6: return "MEA";
case 7: return "ASID";
case 8: return "MEI";
case 10: return "ISPR";
case 11: return "PMR";
case 12: return "ICSR";
case 13: return "INTCFG";
default: break;
}
} else if (selID == 5) {
switch (regID) {
case 0: return "MPM";
case 1: return "MPRC";
case 4: return "MPBRGN";
case 5: return "MPTRGN";
case 8: return "MCA";
case 9: return "MCS";
case 10: return "MCC";
case 11: return "MCR";
default: break;
}
} else if (selID == 6) {
switch (regID) {
case 0: return "MPLA0";
case 1: return "MPUA0";
case 2: return "MPAT0";
case 4: return "MPLA1";
case 5: return "MPUT1";
case 6: return "MPAT1";
case 8: return "MPLA2";
case 9: return "MPUA2";
case 10: return "MPAT2";
case 12: return "MPLA3";
case 13: return "MPUA3";
case 14: return "MPAT3";
case 16: return "MPLA4";
case 17: return "MPUA4";
case 18: return "MPAT4";
case 20: return "MPLA5";
case 21: return "MPUA5";
case 22: return "MPAT5";
case 24: return "MPLA6";
case 25: return "MPUA6";
case 26: return "MPAT6";
case 28: return "MPLA7";
case 29: return "MPUA7";
case 30: return "MPAT7";
default: break;
}
} else if (selID == 7) {
switch (regID) {
case 0: return "MPLA8";
case 1: return "MPUA8";
case 2: return "MPAT8";
case 4: return "MPLA9";
case 5: return "MPUT9";
case 6: return "MPAT9";
case 8: return "MPLA10";
case 9: return "MPUA10";
case 10: return "MPAT10";
case 12: return "MPLA11";
case 13: return "MPUA11";
case 14: return "MPAT11";
case 16: return "MPLA12";
case 17: return "MPUA12";
case 18: return "MPAT12";
case 20: return "MPLA13";
case 21: return "MPUA13";
case 22: return "MPAT13";
case 24: return "MPLA14";
case 25: return "MPUA14";
case 26: return "MPAT14";
case 28: return "MPLA15";
case 29: return "MPUA15";
case 30: return "MPAT15";
default: break;
}
}
return SR[i];
return NULL;
}

typedef struct {
Expand Down Expand Up @@ -286,7 +364,7 @@ static inline int32_t sext32(uint32_t X, unsigned B) {
#define BCOND_DISP_ ((((ctx->w1 >> 4) & 0b111) | (((ctx->w1 >> 11) & 0b11111) << 3)) << 1)
#define BCOND_DISP S32(sext32(BCOND_DISP_, 9))

#define JUMP_DISP_ sext32(ctx->w2 | (ctx->w1 & 0x3f), 22)
#define JUMP_DISP_ sext32((ctx->w2 & 0xfffe) | ((ctx->w1 & 0x3f) << 16), 22)
#define JUMP_DISP S32(JUMP_DISP_)

#define BIT_SUB ((ctx->w1 >> 14) & 0x3)
Expand Down Expand Up @@ -505,7 +583,7 @@ static RzAnalysisLiftedILOp lift_trap(const V850AnalysisContext *ctx) {
return SEQ5(
SETG("EIPC", U32(ctx->pc + 4)),
SETG("EIPSW", VARG("PSW")),
SETGb("ECR", "EICC", EXT2_IMM),
SETGb("ECR", "EICC", U32(EXT2_IMM)),
SETGbs("PSW", 2,
"EP", IL_TRUE,
"ID", IL_TRUE),
Expand Down
7 changes: 3 additions & 4 deletions librz/asm/arch/v850/v850_disas.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -160,19 +160,18 @@ static int decode_jump(const ut8 *instr, int len, struct v850_cmd *cmd) {
return -1;
}

ut16 word2 = rz_read_le16(instr + 2);
ut8 reg = get_reg2(word1);
ut32 disp = (word2 & 0xfffe) | ((word1 & 0x3f) << 16);
if (reg > 0) {
cmd->opcode = V850_JARL;
ut16 word2 = rz_read_at_le16(instr, 2);
ut32 disp = (word2 << 6) | get_reg1(word1);
snprintf(cmd->instr, V850_INSTR_MAXLEN - 1, "%s", "jarl");
snprintf(cmd->operands, V850_INSTR_MAXLEN - 1, "0x%08x, r%d",
disp << 1, reg);
} else {
cmd->opcode = V850_JR;
ut8 reg1 = get_reg1(word1);
snprintf(cmd->instr, V850_INSTR_MAXLEN - 1, "%s", "jr");
snprintf(cmd->operands, V850_INSTR_MAXLEN - 1, "r%d", reg1);
snprintf(cmd->operands, V850_INSTR_MAXLEN - 1, "0x%08x", disp);
}

return 4;
Expand Down

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