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rizinorg · Nov 12, 2024 · 35d8acf · 35d8acf
1 parent fb55209
commit 35d8acf
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Showing 2 changed files with 38 additions and 29 deletions.
diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -30,6 +30,37 @@ static RzAnalysisLiftedILOp op_addi(XtensaContext *ctx) {
 	return SETG(REGN(0), ADD(IREG(1), S32(IMM(2))));
 }
 
+// Fixme: statusflags
+static RzAnalysisLiftedILOp op_add_s(XtensaContext *ctx) {
+	return SETG(REGN(0), UNSIGNED(64, F2BV(FADD(RZ_FLOAT_RMODE_RNA, FLOATV32(IREG(1)), FLOATV32(IREG(2))))));
+}
+
+static RzILOpPure *apply2_range2(RzILOpPure *self, fn_op2 fn, RzILOpPure *x, RzILOpPure *y,
+	unsigned begin1, unsigned begin2, unsigned length) {
+	return DEPOSIT64(
+		self,
+		U64(begin1), U32(length),
+		fn(EXTRACT64(x, U64(begin1), U32(length)), EXTRACT64(y, U64(begin2), U32(length))));
+}
+
+static RzILOpPure *f_add_sub127(RzILOpPure *x, RzILOpPure *y) {
+	return SUB(ADD(x, y), U64(127));
+}
+
+static RzAnalysisLiftedILOp op_addexp_s(XtensaContext *ctx) {
+	return SEQ3(
+		SETL("FRr", apply2_range2(IREG(0), rz_il_op_new_log_xor, IREG(0), IREG(1), 31, 31, 1)),
+		SETL("FRr", apply2_range2(VARL("FRr"), f_add_sub127, IREG(0), IREG(1), 23, 23, 8)),
+		SETG(REGN(0), VARL("FRr")));
+}
+
+static RzAnalysisLiftedILOp op_addexpm_s(XtensaContext *ctx) {
+	return SEQ3(
+		SETL("FRr", apply2_range2(IREG(0), rz_il_op_new_log_xor, IREG(0), IREG(1), 31, 22, 1)),
+		SETL("FRr", apply2_range2(VARL("FRr"), f_add_sub127, IREG(0), IREG(1), 23, 14, 8)),
+		SETG(REGN(0), VARL("FRr")));
+}
+
 static RzAnalysisLiftedILOp op_addx2(XtensaContext *ctx) {
 	return SETG(REGN(0), ADD(SHIFTL0(IREG(1), U32(1)), IREG(2)));
 }
@@ -85,35 +116,11 @@ static RzAnalysisLiftedILOp op_andbc(XtensaContext *ctx) {
 	return SETG(REGN(0), AND(IREG(1), INV(IREG(2))));
 }
 
-// Fixme: statusflags
-static RzAnalysisLiftedILOp op_add_s(XtensaContext *ctx) {
-	return SETG(REGN(0), UNSIGNED(64, F2BV(FADD(RZ_FLOAT_RMODE_RNA, FLOATV32(IREG(1)), FLOATV32(IREG(2))))));
-}
-
-static RzILOpPure *apply2_range2(RzILOpPure *self, fn_op2 fn, RzILOpPure *x, RzILOpPure *y,
-	unsigned begin1, unsigned begin2, unsigned length) {
-	return DEPOSIT64(
-		self,
-		U64(begin1), U32(length),
-		fn(EXTRACT64(x, U64(begin1), U32(length)), EXTRACT64(y, U64(begin2), U32(length))));
-}
-
-static RzILOpPure *f_add_sub127(RzILOpPure *x, RzILOpPure *y) {
-	return SUB(ADD(x, y), U64(127));
-}
-
-static RzAnalysisLiftedILOp op_addexp_s(XtensaContext *ctx) {
-	return SEQ3(
-		SETL("FRr", apply2_range2(IREG(0), rz_il_op_new_log_xor, IREG(0), IREG(1), 31, 31, 1)),
-		SETL("FRr", apply2_range2(VARL("FRr"), f_add_sub127, IREG(0), IREG(1), 23, 23, 8)),
-		SETG(REGN(0), VARL("FRr")));
-}
-
-static RzAnalysisLiftedILOp op_addexpm_s(XtensaContext *ctx) {
-	return SEQ3(
-		SETL("FRr", apply2_range2(IREG(0), rz_il_op_new_log_xor, IREG(0), IREG(1), 31, 22, 1)),
-		SETL("FRr", apply2_range2(VARL("FRr"), f_add_sub127, IREG(0), IREG(1), 23, 14, 8)),
-		SETG(REGN(0), VARL("FRr")));
+static RzAnalysisLiftedILOp op_ball(XtensaContext *ctx) {
+	return BRANCH(
+		IS_ZERO(LOGAND(LOGNOT(IREG(0)), IREG(1))),
+		JMP(U32(IMM(2))),
+		NOP());
 }
 
 #include <rz_il/rz_il_opbuilder_end.h>
@@ -139,6 +146,7 @@ static const fn_analyze_op_il fn_tbl[] = {
 	[XTENSA_INS_ANDBC] = op_andbc,
 	[XTENSA_INS_ANY4] = op_any4,
 	[XTENSA_INS_ANY8] = op_any8,
+	[XTENSA_INS_BALL] = op_ball,
 };
 
 void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -18,3 +18,4 @@ d "andb b2, b3, b1" 102302 0x0 (set b2 (&& (var b3) (var b1)))
 d "andbc b2, b3, b1" 102312 0x0 (set b2 (&& (var b3) (! (var b1))))
 d "any4 b2, b4" 208400 0x0 (set b2 (|| (|| (|| (var b4) (var b5)) (var b6)) (var b7)))
 d "any8 b2, b8" 20a800 0x0 (set b2 (|| (|| (|| (|| (|| (|| (|| (var b8) (var b9)) (var b10)) (var b11)) (var b12)) (var b13)) (var b14)) (var b15)))
+d "ball a2, a1, . +3" 1742ff 0x0 (branch (is_zero (& (~ (var a2)) (var a1))) (jmp (bv 32 0x3)) nop)