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@imbillow
imbillow committed May 10, 2024
1 parent 5b43a80 commit 0d8a749
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Showing 5 changed files with 43 additions and 39 deletions.
22 changes: 11 additions & 11 deletions librz/arch/isa/pic/pic18_analysis.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -24,10 +24,10 @@ typedef struct {

#include "pic18_il.inc"

static void pic18_cond_branch(RzAnalysisOp *aop, ut64 addr, const ut8 *buf) {
static void pic18_cond_branch(RzAnalysisOp *aop, Pic18Op *op) {
aop->type = RZ_ANALYSIS_OP_TYPE_CJMP;
aop->jump = addr + 2 + 2 * (*(ut16 *)buf & 0xff);
aop->fail = addr + aop->size;
aop->jump = op->addr + 2 + 2 * op->n;
aop->fail = op->addr + aop->size;
aop->cycles = 2;
}

Expand Down Expand Up @@ -64,28 +64,28 @@ static int analysis_pic18_op(
aop->type = RZ_ANALYSIS_OP_TYPE_UNK;
break;
case PIC18_OPCODE_BZ: // bz
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_BNZ: // bnz
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_BNC: // bnc
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_BOV: // bov
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_BNOV: // bnov
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_BN: // bn
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_BNN: // bnn
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_BC: // bc
pic18_cond_branch(aop, addr, buf);
pic18_cond_branch(aop, &op);
break;
case PIC18_OPCODE_GOTO: // goto
aop->cycles = 2;
Expand Down
5 changes: 3 additions & 2 deletions librz/arch/isa/pic/pic_pic18.c
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Original file line number Diff line number Diff line change
Expand Up @@ -408,8 +408,9 @@ static const char *rcon_bits[] = {
"pd",
"to",
"ri",
[6] = "lwrt",
[7] = "ipen",
NULL,
"lwrt",
"ipen",
};

static const char *intcon_bits[] = {
Expand Down
50 changes: 25 additions & 25 deletions librz/arch/p/analysis/analysis_pic.c
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Original file line number Diff line number Diff line change
Expand Up @@ -45,54 +45,55 @@ static bool pic_fini(void *user) {
#include "pic/pic_midrange_analysis.inc"
#include "pic/pic18_analysis.inc"

static bool is_pic18(const char *x) {
return RZ_STR_EQ(x, "highend") ||
RZ_STR_EQ(x, "pic") ||
RZ_STR_EQ(x, "pic18");
}

static bool is_pic14_or_pic16(const char *x) {
return RZ_STR_EQ(x, "baseline") ||
RZ_STR_EQ(x, "pic14") ||
RZ_STR_EQ(x, "midrange") ||
RZ_STR_EQ(x, "pic16");
}

static int analysis_pic_op(
RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr,
const ut8 *buf, int len, RzAnalysisOpMask mask) {
if (RZ_STR_ISEMPTY(analysis->cpu) ||
RZ_STR_EQ(analysis->cpu, "pic") ||
RZ_STR_EQ(analysis->cpu, "pic18")) {
if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) {
return analysis_pic18_op(analysis, op, addr, buf, len, mask);
}

if (RZ_STR_EQ(analysis->cpu, "baseline") ||
RZ_STR_EQ(analysis->cpu, "midrange")) {
if (is_pic14_or_pic16(analysis->cpu)) {
return analysis_pic_midrange_op(analysis, op, addr, buf, len, mask);
}
return -1;
}

static char *analysis_pic_get_reg_profile(RzAnalysis *analysis) {
if (RZ_STR_ISEMPTY(analysis->cpu) ||
RZ_STR_EQ(analysis->cpu, "pic") ||
RZ_STR_EQ(analysis->cpu, "pic18")) {
if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) {
return analysis_pic_pic18_get_reg_profile(analysis);
}

if (RZ_STR_EQ(analysis->cpu, "baseline") ||
RZ_STR_EQ(analysis->cpu, "midrange")) {
if (is_pic14_or_pic16(analysis->cpu)) {
return analysis_pic_midrange_get_reg_profile(analysis);
}
return NULL;
}

static RzAnalysisILConfig *pic_il_config(RzAnalysis *a) {
if (a->cpu && strcasecmp(a->cpu, "baseline") == 0) {
// TODO: We are using the midrange il config as the baseline
return pic_midrange_il_config(a);
}
if (a->cpu && strcasecmp(a->cpu, "midrange") == 0) {
return pic_midrange_il_config(a);
static RzAnalysisILConfig *pic_il_config(RzAnalysis *analysis) {
if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) {
return pic18_il_config(analysis);
}
if (a->cpu && (strcasecmp(a->cpu, "pic18") == 0 || RZ_STR_EQ(a->cpu, "pic"))) {
return pic18_il_config(a);
if (is_pic14_or_pic16(analysis->cpu)) {
return pic_midrange_il_config(analysis);
}
return NULL;
}

static int pic_archinfo(RzAnalysis *a, RzAnalysisInfoType query) {
if (RZ_STR_ISEMPTY(a->cpu) ||
RZ_STR_EQ(a->cpu, "pic") ||
RZ_STR_EQ(a->cpu, "pic18")) {
static int pic_archinfo(RzAnalysis *analysis, RzAnalysisInfoType query) {
if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) {
switch (query) {
case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2;
case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: return 4;
Expand All @@ -103,8 +104,7 @@ static int pic_archinfo(RzAnalysis *a, RzAnalysisInfoType query) {
}
}

if (RZ_STR_EQ(a->cpu, "baseline") ||
RZ_STR_EQ(a->cpu, "midrange")) {
if (is_pic14_or_pic16(analysis->cpu)) {
switch (query) {
case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2;
case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: return 2;
Expand Down
2 changes: 1 addition & 1 deletion librz/arch/p/asm/asm_pic.c
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ static int asm_pic_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) {
RzAsmPlugin rz_asm_plugin_pic = {
.name = "pic",
.arch = "pic",
.cpus = "pic18,baseline,midrange",
.cpus = "pic18,pic16,pic14,pic12,pic10,highend,midrange,baseline",
.bits = 8,
.license = "LGPL3",
.desc = "PIC disassembler",
Expand Down
3 changes: 3 additions & 0 deletions test/db/analysis/pic
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Original file line number Diff line number Diff line change
Expand Up @@ -109,5 +109,8 @@ stkptr = 0x00
_sram = 0x00
_stack = 0x00
_skip = 0x00
wregs = 0x00
statuss = 0x00
bsrs = 0x00
EOF
RUN

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