Refactor chip reset #597
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Refactor chip reset #597
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This simplifies, clarifies and fixes the reset functionality. Until now the model conflates reset and initialisation, and does way more than it should on reset. The RISC-V spec only requires a very small number of things to be reset. This change: 1. Renames the `init` functions to `reset`, to clarify that they correspond to resetting the chip. 2. Removes the `ext_init` and `ext_rvfi_init` functions. The latter is not used and the former is only used by the old CHERI code. 2. Removes the reset of the X and F registers. These are non-reset. 3. Removes the reset of various CSRs that are non-reset (`mip`, `mie`, `mideleg`, `mtvec`, `mepc`, etc). 4. Adds reset of `mstatus[MIE]` and `mstatus[MPRV]`. As far as I can see they were missing. 5. Add one-time init of `mhartid` etc to 0. I didn't remove the vector register resets yet. That needs a bigger refactor. Also note that currently there is no way to actually do a chip reset mid-simulation, but that will be needed eventually.
Test Results396 tests ±0 173 ✅ - 223 0s ⏱️ ±0s For more details on these failures, see this check. Results for commit f2bf830. ± Comparison against base commit 2b65a0d. |
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This simplifies, clarifies and fixes the reset functionality.
Until now the model conflates reset and initialisation, and does way more than it should on reset. The RISC-V spec only requires a very small number of things to be reset.
This change:
initfunctions toreset, to clarify that they correspond to resetting the chip.ext_initandext_rvfi_initfunctions. The latter is not used and the former is only used by the old CHERI code.mip,mie,mideleg,mtvec,mepc, etc).mstatus[MIE]andmstatus[MPRV]. As far as I can see they were missing.mhartidetc to 0.I didn't remove the vector register resets yet. That needs a bigger refactor.
Also note that currently there is no way to actually do a chip reset mid-simulation, but that will be needed eventually.