Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add read-only CSR MCONFIGPTR #422

Merged
merged 1 commit into from
Apr 24, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions model/riscv_csr_map.sail
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@ mapping clause csr_name_map = 0xF11 <-> "mvendorid"
mapping clause csr_name_map = 0xF12 <-> "marchid"
mapping clause csr_name_map = 0xF13 <-> "mimpid"
mapping clause csr_name_map = 0xF14 <-> "mhartid"
mapping clause csr_name_map = 0xF15 <-> "mconfigptr"
/* machine trap setup */
mapping clause csr_name_map = 0x300 <-> "mstatus"
mapping clause csr_name_map = 0x301 <-> "misa"
Expand Down
1 change: 1 addition & 0 deletions model/riscv_insts_zicsr.sail
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ function readCSR csr : csreg -> xlenbits = {
(0xF12, _) => marchid,
(0xF13, _) => mimpid,
(0xF14, _) => mhartid,
(0xF15, _) => mconfigptr,
(0x300, _) => mstatus.bits,
(0x301, _) => misa.bits,
(0x302, _) => medeleg.bits,
Expand Down
2 changes: 2 additions & 0 deletions model/riscv_sys_control.sail
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
0xf12 => p == Machine, // marchdid
0xf13 => p == Machine, // mimpid
0xf14 => p == Machine, // mhartid
0xf15 => p == Machine, // mconfigptr
/* machine mode: trap setup */
0x300 => p == Machine, // mstatus
0x301 => p == Machine, // misa
Expand Down Expand Up @@ -477,6 +478,7 @@ function init_sys() -> unit = {
cur_privilege = Machine;

mhartid = zero_extend(0b0);
mconfigptr = zero_extend(0b0);

misa[MXL] = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
misa[A] = 0b1; /* atomics */
Expand Down
1 change: 1 addition & 0 deletions model/riscv_sys_regs.sail
Original file line number Diff line number Diff line change
Expand Up @@ -510,6 +510,7 @@ register mimpid : xlenbits
register marchid : xlenbits
/* TODO: this should be readonly, and always 0 for now */
register mhartid : xlenbits
register mconfigptr : xlenbits

/* S-mode registers */

Expand Down
Loading