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Remove duplicate shift definitions #305

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merged 1 commit into from
Oct 26, 2023
Merged

Remove duplicate shift definitions #305

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4 changes: 2 additions & 2 deletions model/riscv_analysis.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,7 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
SHIFTW(imm, rs, rd, op) => {
SHIFTIWOP(imm, rs, rd, op) => {
if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
Expand Down Expand Up @@ -346,7 +346,7 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
SHIFTW(imm, rs, rd, op) => {
SHIFTIWOP(imm, rs, rd, op) => {
if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
Expand Down
46 changes: 4 additions & 42 deletions model/riscv_insts_base.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -504,44 +504,6 @@ mapping clause assembly = ADDIW(imm, rs1, rd)
<-> "addiw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)
if sizeof(xlen) == 64

/* ****************************************************************** */
union clause ast = SHIFTW : (bits(5), regidx, regidx, sop)

mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SLLI)
if sizeof(xlen) == 64
<-> 0b0000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011
if sizeof(xlen) == 64
mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SRLI)
if sizeof(xlen) == 64
<-> 0b0000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
if sizeof(xlen) == 64
mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SRAI)
if sizeof(xlen) == 64
<-> 0b0100000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
if sizeof(xlen) == 64

function clause execute (SHIFTW(shamt, rs1, rd, op)) = {
let rs1_val = (X(rs1))[31..0];
let result : bits(32) = match op {
RISCV_SLLI => rs1_val << shamt,
RISCV_SRLI => rs1_val >> shamt,
RISCV_SRAI => shift_right_arith32(rs1_val, shamt)
};
X(rd) = sign_extend(result);
RETIRE_SUCCESS
}

mapping shiftw_mnemonic : sop <-> string = {
RISCV_SLLI <-> "slli",
RISCV_SRLI <-> "srli",
RISCV_SRAI <-> "srai"
}

mapping clause assembly = SHIFTW(shamt, rs1, rd, op)
if sizeof(xlen) == 64
<-> shiftw_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt)
if sizeof(xlen) == 64

/* ****************************************************************** */
union clause ast = RTYPEW : (regidx, regidx, regidx, ropw)

Expand Down Expand Up @@ -610,11 +572,11 @@ mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRAIW)
if sizeof(xlen) == 64

function clause execute (SHIFTIWOP(shamt, rs1, rd, op)) = {
let rs1_val = X(rs1);
let rs1_val = (X(rs1))[31..0];
let result : bits(32) = match op {
RISCV_SLLIW => rs1_val[31..0] << shamt,
RISCV_SRLIW => rs1_val[31..0] >> shamt,
RISCV_SRAIW => shift_right_arith32(rs1_val[31..0], shamt)
RISCV_SLLIW => rs1_val << shamt,
RISCV_SRLIW => rs1_val >> shamt,
RISCV_SRAIW => shift_right_arith32(rs1_val, shamt)
};
X(rd) = sign_extend(result);
RETIRE_SUCCESS
Expand Down
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