add srmcfg CSR introduced by Ssqosid

model/riscv_csr_map.sail

@@ -176,6 +176,8 @@ mapping clause csr_name_map = 0x00F  <-> "vcsr"
 mapping clause csr_name_map = 0xC20  <-> "vl"
 mapping clause csr_name_map = 0xC21  <-> "vtype"
 mapping clause csr_name_map = 0xC22  <-> "vlenb"
+/* Sqosid csrs */
+mapping clause csr_name_map = 0x181  <-> "srmcfg"
 /* Smstateen csrs */
 mapping clause csr_name_map = 0x30C  <-> "mstateen0"
 mapping clause csr_name_map = 0x31C  <-> "mstateen0h"

model/riscv_insts_zicsr.sail

@@ -38,10 +38,10 @@ function readCSR csr : csreg -> xlenbits = {
     (0x305,  _) => get_mtvec(),
     (0x306,  _) => zero_extend(mcounteren.bits),
     (0x30A,  _) => menvcfg.bits[sizeof(xlen) - 1 .. 0],
-    (0x30C,  _) => mstateen0.bits()[sizeof(xlen) - 1 .. 0],
+    (0x30C,  _) => mstateen0.bits[sizeof(xlen) - 1 .. 0],
     (0x310, 32) => mstatush.bits,
     (0x31A, 32) => menvcfg.bits[63 .. 32],
-    (0x31C, 32) => mstateen0.bits()[63 .. 32],
+    (0x31C, 32) => mstateen0.bits[63 .. 32],
     (0x320,  _) => zero_extend(mcountinhibit.bits),
 
     (0x340,  _) => mscratch,
@@ -90,6 +90,7 @@ function readCSR csr : csreg -> xlenbits = {
     (0x143,  _) => stval,
     (0x144,  _) => lower_mip(mip, mideleg).bits,
     (0x180,  _) => satp,
+    (0x181,  _) => srmcfg.bits(),
 
     /* user mode counters */
     (0xC00,  _) => mcycle[(sizeof(xlen) - 1) .. 0],
@@ -174,6 +175,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
     (0x143,  _) => { stval = value; Some(stval) },
     (0x144,  _) => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits) },
     (0x180,  _) => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) },
+    (0x181,  _) => { srmcfg = legalize_srmcfg(srmcfg, value); Some(srmcfg.bits()) },
 
     /* user mode: seed (entropy source). writes are ignored */
     (0x015,  _) => write_seed_csr(),

model/riscv_sys_control.sail

@@ -79,6 +79,11 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
     /* supervisor mode: address translation */
     0x180 => haveSupMode() & (p == Machine | p == Supervisor), // satp
 
+    /* supervisor mode: resource management configurations */
+    0x181 => haveSsqosid() & ((p == Machine) |
+                              ((p == Supervisor) & haveSmstateen() & (mstateen0.PRIV_V1P14() == 0b1)) |
+                              ((p == Supervisor) & not(haveSmstateen()))), // srmcfg
+
     /* user mode: counters */
     0xC00 => haveUsrMode(),    // cycle
     0xC01 => haveUsrMode(),    // time
@@ -530,7 +535,7 @@ function init_sys() -> unit = {
 
   menvcfg.bits = zero_extend(0b0);
   senvcfg.bits = zero_extend(0b0);
-  mstateen0->bits() = zero_extend(0b0);
+  mstateen0.bits = zero_extend(0b0);
 
   /* initialize vector csrs */
   elen               = 0b1; /* ELEN=64 as the common case */
@@ -555,6 +560,8 @@ function init_sys() -> unit = {
   // PMP's L and A fields are set to 0 on reset.
   init_pmp();
 
+  srmcfg->RCID()     = 0b000000000000;
+
   // log compatibility with spike
   if   get_config_print_reg()
   then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits) ^ " (input: " ^ BitStr(zero_extend(0b0) : xlenbits) ^ ")")

model/riscv_sys_regs.sail

@@ -866,18 +866,24 @@ function is_fiom_active() -> bool = {
 }
 
 bitfield Mstateen0 : bits(64) = {
-  // controls to new state introduced by the following small extensions of Priv-1.14-era:
-  PRIV114  : 55
+  // PRIV_V1P14 control access to various state added concurrent
+  // with Priv Specification version 1.14. The following is the
+  // list of state currently defined to be controlled by this bit:
+  //   - CSR srmcfg introduced by Ssqosid extension
+  PRIV_V1P14  : 55
 }
+
 register mstateen0 : Mstateen0
-// If any extension controlled by PRIV114 bit in mstateen0 is present
-// then PRIV114 bit is present
-function havePriv114Extensions() -> bool = {
+
+// If any extension controlled by PRIV_V1P14 bit in mstateen0 are
+// present then the PRIV_V1P14 bit in mstateen0 is present
+function have_PRIV_V1P14_Extensions() -> bool = {
   haveSsqosid()
 }
+
 function legalize_mstateen0(o : Mstateen0, v : bits(64)) -> Mstateen0 = {
   let v = Mk_Mstateen0(v);
-  let o = update_PRIV114(o, if havePriv114Extensions() then v.PRIV114() else 0b0);
+  let o = update_PRIV_V1P14(o, if have_PRIV_V1P14_Extensions() then v.PRIV_V1P14() else 0b0);
   // Other extensions are not implemented yet so all other fields are read only zero.
   o
 }
@@ -965,4 +971,19 @@ val get_vtype_vma : unit -> agtype
 function get_vtype_vma() = decode_agtype(vtype[vma])
 
 val get_vtype_vta : unit -> agtype
+
 function get_vtype_vta() = decode_agtype(vtype[vta])
+
+/* srmcfg CSR introduced by Ssqosid */
+bitfield Srmcfg : xlenbits = {
+  MCID : 27 .. 16,
+  RCID : 11 .. 0
+}
+
+register srmcfg : Srmcfg
+
+function legalize_srmcfg(s : Srmcfg, v : xlenbits) -> Srmcfg = {
+  let s = update_MCID(s, v[27 .. 16]);
+  let s = update_RCID(s, v[11 .. 0]);
+  s
+}