Merge branch 'master' of https://github.com/rez5427/sail-riscv

riscv · Oct 10, 2024 · 60f8ae6 · 60f8ae6
2 parents 520f019 + f7192a6
commit 60f8ae6
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Showing 4 changed files with 3 additions and 17 deletions.
diff --git a/generated_definitions/ast/riscv-ast-raw.txt b/generated_definitions/ast/riscv-ast-raw.txt
diff --git a/model/riscv_insts_vext_mem.sail b/model/riscv_insts_vext_mem.sail
@@ -146,7 +146,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)
   var trimmed : bool = false;
   foreach (i from 0 to (num_elem - 1)) {
     if not(trimmed) then {
-      if vm_val[i] then { /* active segments */
+      if mask[i] then { /* active segments */
         foreach (j from 0 to (nf - 1)) {
           let elem_offset = (i * nf + j) * load_width_bytes;
           match ext_data_get_addr(rs1, to_bits(xlen, elem_offset), Read(Data), load_width_bytes) {
@@ -247,7 +247,7 @@ function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem)
   let mask    : vector('n, bool) = init_masked_source(num_elem, EMUL_pow, vm_val);
 
   foreach (i from 0 to (num_elem - 1)) {
-    if vm_val[i] then { /* active segments */
+    if mask[i] then { /* active segments */
       vstart = to_bits(16, i);
       foreach (j from 0 to (nf - 1)) {
         let elem_offset = (i * nf + j) * load_width_bytes;
@@ -622,7 +622,7 @@ function clause execute(VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3)) = {
   process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3)
 }
 
-mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3)
+mapping clause assembly = VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3)
   <-> "vsox" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm)
 
 /* ***************** Vector Load Unit-Stride Whole Register (vm=0b1, mop=0b00, lumop=0b01000) ****************** */

diff --git a/model/riscv_insts_vext_utils.sail b/model/riscv_insts_vext_utils.sail
@@ -418,7 +418,6 @@ function unsigned_saturation(len, elem) = {
     vcsr[vxsat] = 0b1;
     ones('m)
   } else {
-    vcsr[vxsat] = 0b0;
     elem['m - 1 .. 0]
   }
 }
@@ -433,7 +432,6 @@ function signed_saturation(len, elem) = {
     vcsr[vxsat] = 0b1;
     0b1 @ zeros('m - 1)
   } else {
-    vcsr[vxsat] = 0b0;
     elem['m - 1 .. 0]
   };
 }

diff --git a/model/riscv_vmem_common.sail b/model/riscv_vmem_common.sail
@@ -101,14 +101,3 @@ let sv57_params : SV_Params = struct {
        pte_PPN_j_size_bits = 9
 }
 */
-
-// This 'undefined_SV_Params()' function is not used anywhere, but is
-// currently (2023-12) needed to work around an issue where Sail tries
-// to figure out how it could do
-//     let x : SV_Params = undefined
-// even though the code never does this.  This has been fixed in Sail.
-// The fix will become available in a new Sail release, at which point
-// this function can be deleted (TODO).
-// PRIVATE
-val      undefined_SV_Params : unit -> SV_Params
-function undefined_SV_Params() = sv32_params