hook jalr

riscv · Nov 26, 2023 · 3ba53b6 · 3ba53b6
1 parent 044d6f2
commit 3ba53b6
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diff --git a/model/riscv_jalr_rmem.sail b/model/riscv_jalr_rmem.sail
@@ -68,6 +68,9 @@
 /*  SUCH DAMAGE.                                                                         */
 /*=======================================================================================*/
 
+/* Zicfilp : Update ELP state */
+val zicfilp_update_elp : (regidx, regidx) -> unit
+
 /* The definition for the memory model. */
 
 function clause execute (RISCV_JALR(imm, rs1, rd)) = {
@@ -76,5 +79,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
   X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */
   let newPC : xlenbits = X(rs1) + sign_extend(imm);
   nextPC = [newPC with 0 = bitzero];  /* Clear newPC[0] */
+  /* update ELP if Zicfilp is active */
+  zicfilp_update_elp(rs1, rd);
   RETIRE_SUCCESS
 }
diff --git a/model/riscv_jalr_seq.sail b/model/riscv_jalr_seq.sail
@@ -68,6 +68,9 @@
 /*  SUCH DAMAGE.                                                                         */
 /*=======================================================================================*/
 
+/* Zicfilp : Update ELP state */
+val zicfilp_update_elp : (regidx, regidx) -> unit
+
 /* The definition for the sequential model. */
 
 function clause execute (RISCV_JALR(imm, rs1, rd)) = {
@@ -92,6 +95,8 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
       } else {
         X(rd) = get_next_pc();
         set_next_pc(target);
+        /* update ELP if Zicfilp is active */
+        zicfilp_update_elp(rs1, rd);
         RETIRE_SUCCESS
       }
     }