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Separate Zifencei extension from base ISA
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The `fence.i` instruction has been part of the Zifencei extension instead of the base ISA since version 2.1 in 2019. This updates the model to separate it into its own file and gates it on `extensionEnabled(Ext_Zifencei)`.
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jordancarlin authored Oct 23, 2024
1 parent 633a8c7 commit 1d152e8
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Showing 3 changed files with 25 additions and 12 deletions.
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ SAIL_VLEN := riscv_vlen.sail

# Instruction sources, depending on target
SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_zifencei.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail

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11 changes: 0 additions & 11 deletions model/riscv_insts_base.sail
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Expand Up @@ -607,17 +607,6 @@ function clause execute (FENCE_TSO(pred, succ)) = {
mapping clause assembly = FENCE_TSO(pred, succ)
<-> "fence.tso" ^ spc() ^ fence_bits(pred) ^ sep() ^ fence_bits(succ)

/* ****************************************************************** */
union clause ast = FENCEI : unit

mapping clause encdec = FENCEI()
<-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000 @ 0b0001111

/* fence.i is a nop for the memory model */
function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS }

mapping clause assembly = FENCEI() <-> "fence.i"

/* ****************************************************************** */
union clause ast = ECALL : unit

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24 changes: 24 additions & 0 deletions model/riscv_insts_zifencei.sail
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

/* ****************************************************************** */
/* This file specifies the instructions in the 'Zifencei' extension. */

/* ****************************************************************** */
enum clause extension = Ext_Zifencei
function clause extensionEnabled(Ext_Zifencei) = true

union clause ast = FENCEI : unit

mapping clause encdec = FENCEI() if extensionEnabled(Ext_Zifencei)
<-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000 @ 0b0001111 if extensionEnabled(Ext_Zifencei)

/* fence.i is a nop for the memory model */
function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS }

mapping clause assembly = FENCEI() <-> "fence.i"

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