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Merge pull request #517 from jordancarlin/zc_extensions
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Use Zc* extensions instead of just the C extension
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@billmcspadden-riscv
billmcspadden-riscv authored Aug 12, 2024
2 parents d538d45 + b4a6db0 commit 05b845c
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Showing 9 changed files with 105 additions and 120 deletions.
6 changes: 3 additions & 3 deletions Makefile
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Expand Up @@ -23,9 +23,9 @@ SAIL_VLEN := riscv_vlen.sail

# Instruction sources, depending on target
SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_cfext.sail
SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_cdext.sail
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail

SAIL_DEFAULT_INST += riscv_insts_svinval.sail

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2 changes: 1 addition & 1 deletion model/riscv_fetch.sail
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Expand Up @@ -19,7 +19,7 @@ function fetch() -> FetchResult =
match ext_fetch_check_pc(PC, PC) {
Ext_FetchAddr_Error(e) => F_Ext_Error(e),
Ext_FetchAddr_OK(use_pc) => {
if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_C))))
if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
then F_Error(E_Fetch_Addr_Align(), PC)
else match translateAddr(use_pc, Execute()) {
TR_Failure(e, _) => F_Error(e, PC),
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2 changes: 1 addition & 1 deletion model/riscv_fetch_rvfi.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ function fetch() -> FetchResult = {
Ext_FetchAddr_Error(e) => F_Ext_Error(e),
Ext_FetchAddr_OK(use_pc) => {
/* then check PC alignment */
if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_C))))
if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
then F_Error(E_Fetch_Addr_Align(), PC)
else match translateAddr(use_pc, Execute()) {
TR_Failure(e, _) => F_Error(e, PC),
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7 changes: 5 additions & 2 deletions model/riscv_insts_base.sail
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Expand Up @@ -12,6 +12,9 @@
enum clause extension = Ext_C
function clause extensionEnabled(Ext_C) = misa[C] == 0b1

enum clause extension = Ext_Zca
function clause extensionEnabled(Ext_Zca) = extensionEnabled(Ext_C)

/* ****************************************************************** */
union clause ast = UTYPE : (bits(20), regidx, uop)

Expand Down Expand Up @@ -69,7 +72,7 @@ function clause execute (RISCV_JAL(imm, rd)) = {
},
Ext_ControlAddr_OK(target) => {
/* Perform standard alignment check */
if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C))
if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca))
then {
handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL
Expand Down Expand Up @@ -133,7 +136,7 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) = {
RETIRE_FAIL
},
Ext_ControlAddr_OK(target) => {
if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C)) then {
if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca)) then {
handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL;
} else {
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143 changes: 71 additions & 72 deletions model/riscv_insts_cext.sail → model/riscv_insts_zca.sail
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Large diffs are not rendered by default.

33 changes: 10 additions & 23 deletions model/riscv_insts_cdext.sail → model/riscv_insts_zcd.sail
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Expand Up @@ -6,20 +6,13 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

/* ********************************************************************* */
/* This file specifies the compressed floating-point instructions.
*
* These instructions are only legal if misa[C] and misa[D]
* are set.
*/
enum clause extension = Ext_Zcd
function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (sizeof(xlen) == 32 | sizeof(xlen) == 64)

/* ****************************************************************** */
union clause ast = C_FLDSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
<-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd) if extensionEnabled(Ext_Zcd)
<-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10 if extensionEnabled(Ext_Zcd)

function clause execute (C_FLDSP(uimm, rd)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
Expand All @@ -34,10 +27,8 @@ mapping clause assembly = C_FLDSP(uimm, rd)
/* ****************************************************************** */
union clause ast = C_FSDSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
<-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2) if extensionEnabled(Ext_Zcd)
<-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10 if extensionEnabled(Ext_Zcd)

function clause execute (C_FSDSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
Expand All @@ -52,10 +43,8 @@ mapping clause assembly = C_FSDSP(uimm, rs2)
/* ****************************************************************** */
union clause ast = C_FLD : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
<-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd) if extensionEnabled(Ext_Zcd)
<-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00 if extensionEnabled(Ext_Zcd)

function clause execute (C_FLD(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
Expand All @@ -72,10 +61,8 @@ mapping clause assembly = C_FLD(uimm, rsc, rdc)
/* ****************************************************************** */
union clause ast = C_FSD : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2)
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
<-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00
if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2) if extensionEnabled(Ext_Zcd)
<-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00 if extensionEnabled(Ext_Zcd)

function clause execute (C_FSD(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
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28 changes: 12 additions & 16 deletions model/riscv_insts_cfext.sail → model/riscv_insts_zcf.sail
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Expand Up @@ -14,12 +14,14 @@
*/

/* ****************************************************************** */

enum clause extension = Ext_Zcf
function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & sizeof(xlen) == 32

union clause ast = C_FLWSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FLWSP(ui76 @ ui5 @ ui42, rd)
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
<-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
mapping clause encdec_compressed = C_FLWSP(ui76 @ ui5 @ ui42, rd) if extensionEnabled(Ext_Zcf)
<-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10 if extensionEnabled(Ext_Zcf)

function clause execute (C_FLWSP(imm, rd)) = {
let imm : bits(12) = zero_extend(imm @ 0b00);
Expand All @@ -34,10 +36,8 @@ mapping clause assembly = C_FLWSP(imm, rd)
/* ****************************************************************** */
union clause ast = C_FSWSP : (bits(6), regidx)

mapping clause encdec_compressed = C_FSWSP(ui76 @ ui52, rs2)
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
<-> 0b111 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
mapping clause encdec_compressed = C_FSWSP(ui76 @ ui52, rs2) if extensionEnabled(Ext_Zcf)
<-> 0b111 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10 if extensionEnabled(Ext_Zcf)

function clause execute (C_FSWSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
Expand All @@ -52,10 +52,8 @@ mapping clause assembly = C_FSWSP(uimm, rs2)
/* ****************************************************************** */
union clause ast = C_FLW : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FLW(ui6 @ ui53 @ ui2, rs1, rd)
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
<-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
mapping clause encdec_compressed = C_FLW(ui6 @ ui53 @ ui2, rs1, rd) if extensionEnabled(Ext_Zcf)
<-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00 if extensionEnabled(Ext_Zcf)

function clause execute (C_FLW(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
Expand All @@ -72,10 +70,8 @@ mapping clause assembly = C_FLW(uimm, rsc, rdc)
/* ****************************************************************** */
union clause ast = C_FSW : (bits(5), cregidx, cregidx)

mapping clause encdec_compressed = C_FSW(ui6 @ ui53 @ ui2, rs1, rs2)
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
<-> 0b111 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00
if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
mapping clause encdec_compressed = C_FSW(ui6 @ ui53 @ ui2, rs1, rs2) if extensionEnabled(Ext_Zcf)
<-> 0b111 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00 if extensionEnabled(Ext_Zcf)

function clause execute (C_FSW(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
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2 changes: 1 addition & 1 deletion model/riscv_jalr_seq.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
},
Ext_ControlAddr_OK(addr) => {
let target = [addr with 0 = bitzero]; /* clear addr[0] */
if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C)) then {
if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca)) then {
handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL
} else {
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2 changes: 1 addition & 1 deletion model/riscv_step.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ function step(step_no : int) -> bool = {
print_instr("[" ^ dec_str(step_no) ^ "] [" ^ to_str(cur_privilege) ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ to_str(ast));
};
/* check for RVC once here instead of every RVC execute clause. */
if extensionEnabled(Ext_C) then {
if extensionEnabled(Ext_Zca) then {
nextPC = PC + 2;
(execute(ast), true)
} else {
Expand Down

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