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Use MemoryAccessInfo instead of Inst for passing requests between cac…
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…hes and MSS (#144)

As part of #143 use MemoryAccessInfo as the standard transaction type
for making memory requests outside of the core, instead of instructions.

This paves way for adding an instruction cache, as well as prefetching
and more complicated memory subsystems where requests do not always
correspond to a particularly instruction.

Changes are minor, mostly just renaming.

Co-authored-by: Daniel Bone <[email protected]>
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danbone and Daniel Bone authored Jan 31, 2024
1 parent ce29ae2 commit db6c2f1
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Showing 13 changed files with 166 additions and 163 deletions.
14 changes: 7 additions & 7 deletions core/DCache.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ namespace olympia {
(CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getAckFromL2Cache_, uint32_t));

in_l2cache_resp_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, InstPtr));
(CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, MemoryAccessInfoPtr));

// DL1 cache config
const uint32_t l1_line_size = p->l1_line_size;
Expand Down Expand Up @@ -84,27 +84,27 @@ namespace olympia {
if(!busy_) {
busy_ = true;
cache_pending_inst_ = memory_access_info_ptr;
out_l2cache_req_.send(cache_pending_inst_->getInstPtr());
out_l2cache_req_.send(cache_pending_inst_);

// Set the --dcache_l2cache_credits_ here.
}
}
out_lsu_lookup_ack_.send(memory_access_info_ptr);
}

void DCache::getRespFromL2Cache_(const InstPtr &inst_ptr) {
void DCache::getRespFromL2Cache_(const MemoryAccessInfoPtr &memory_access_info_ptr) {
out_lsu_lookup_req_.send(cache_pending_inst_);
reloadCache_(inst_ptr->getRAdr());
reloadCache_(memory_access_info_ptr->getPhyAddr());
cache_pending_inst_.reset();
busy_ = false;
}

void DCache::getAckFromL2Cache_(const uint32_t &ack) {
// When DCache sends the request to L2Cache for a miss,
// This bool will be set to false, and Dcache should wait for ack from
// This bool will be set to false, and Dcache should wait for ack from
// L2Cache notifying DCache that there is space in it's dcache request buffer
//
// Set it to true so that the following misses from DCache can be sent out to L2Cache.
//
// Set it to true so that the following misses from DCache can be sent out to L2Cache.
dcache_l2cache_credits_ = ack;
}

Expand Down
8 changes: 5 additions & 3 deletions core/DCache.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ namespace olympia

void getAckFromL2Cache_(const uint32_t & ack);

void getRespFromL2Cache_(const InstPtr & inst_ptr);
void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr);

using L1Handle = CacheFuncModel::Handle;
L1Handle l1_cache_;
Expand All @@ -61,7 +61,8 @@ namespace olympia

sparta::DataInPort<uint32_t> in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1};

sparta::DataInPort<InstPtr> in_l2cache_resp_{&unit_port_set_, "in_l2cache_resp", 1};
sparta::DataInPort<MemoryAccessInfoPtr> in_l2cache_resp_{&unit_port_set_,
"in_l2cache_resp", 1};

////////////////////////////////////////////////////////////////////////////////
// Output Ports
Expand All @@ -74,7 +75,8 @@ namespace olympia
sparta::DataOutPort<MemoryAccessInfoPtr> out_lsu_lookup_req_{&unit_port_set_,
"out_lsu_lookup_req", 1};

sparta::DataOutPort<InstPtr> out_l2cache_req_{&unit_port_set_, "out_l2cache_req", 0};
sparta::DataOutPort<MemoryAccessInfoPtr> out_l2cache_req_{&unit_port_set_,
"out_l2cache_req", 0};

////////////////////////////////////////////////////////////////////////////////
// Events
Expand Down
11 changes: 6 additions & 5 deletions core/MemoryAccessInfo.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,8 @@ namespace olympia

MemoryAccessInfo() = delete;

MemoryAccessInfo(const MemoryAccessInfo &rhs) = default;

MemoryAccessInfo(const InstPtr & inst_ptr) :
ldst_inst_ptr_(inst_ptr),
phy_addr_ready_(false),
Expand Down Expand Up @@ -92,6 +94,10 @@ namespace olympia

bool getPhyAddrStatus() const { return phy_addr_ready_; }

uint64_t getPhyAddr() const { return ldst_inst_ptr_->getRAdr(); }

sparta::memory::addr_t getVAddr() const { return ldst_inst_ptr_->getTargetVAddr(); }

void setSrcUnit(const ArchUnit & src_unit) { src_ = src_unit; }

const ArchUnit & getSrcUnit() const { return src_; }
Expand Down Expand Up @@ -158,11 +164,6 @@ namespace olympia
// Not for functional/performance purpose)
MemoryAccessInfoPtr next_req_ = nullptr;

// Scoreboards
using ScoreboardViews =
std::array<std::unique_ptr<sparta::ScoreboardView>, core_types::N_REGFILES>;
ScoreboardViews scoreboard_views_;

LoadStoreInstIterator issue_queue_iterator_;
LoadStoreInstIterator replay_queue_iterator_;
};
Expand Down
16 changes: 8 additions & 8 deletions mss/BIU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ namespace olympia_mss
biu_latency_(p->biu_latency)
{
in_biu_req_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(BIU, receiveReqFromL2Cache_, olympia::InstPtr));
(CREATE_SPARTA_HANDLER_WITH_DATA(BIU, receiveReqFromL2Cache_, olympia::MemoryAccessInfoPtr));

in_mss_ack_sync_.registerConsumerHandler
(CREATE_SPARTA_HANDLER_WITH_DATA(BIU, getAckFromMSS_, bool));
Expand All @@ -41,9 +41,9 @@ namespace olympia_mss
}

// Receive new BIU request from L2Cache
void BIU::receiveReqFromL2Cache_(const olympia::InstPtr & inst_ptr)
void BIU::receiveReqFromL2Cache_(const olympia::MemoryAccessInfoPtr & memory_access_info_ptr)
{
appendReqQueue_(inst_ptr);
appendReqQueue_(memory_access_info_ptr);

// Schedule BIU request handling event only when:
// (1)BIU is not busy, and (2)Request queue is not empty
Expand Down Expand Up @@ -81,9 +81,9 @@ namespace olympia_mss
void BIU::handle_MSS_Ack_()
{
out_biu_resp_.send(biu_req_queue_.front(), biu_latency_);

biu_req_queue_.pop_front();

// Send out the ack to L2Cache through , we just created space in biu_req_queue_
ev_handle_biu_l2cache_ack_.schedule(sparta::Clock::Cycle(0));
biu_busy_ = false;
Expand Down Expand Up @@ -113,7 +113,7 @@ namespace olympia_mss
}

// Handle ack backto L2Cache
void BIU::handle_BIU_L2Cache_Ack_()
void BIU::handle_BIU_L2Cache_Ack_()
{
uint32_t available_slots = biu_req_queue_size_ - biu_req_queue_.size();
out_biu_ack_.send(available_slots);
Expand All @@ -126,12 +126,12 @@ namespace olympia_mss
////////////////////////////////////////////////////////////////////////////////

// Append BIU request queue
void BIU::appendReqQueue_(const olympia::InstPtr& inst_ptr)
void BIU::appendReqQueue_(const olympia::MemoryAccessInfoPtr& memory_access_info_ptr)
{
sparta_assert(biu_req_queue_.size() <= biu_req_queue_size_ ,"BIU request queue overflows!");

// Push new requests from back
biu_req_queue_.emplace_back(inst_ptr);
biu_req_queue_.emplace_back(memory_access_info_ptr);

ILOG("Append BIU request queue!");
}
Expand Down
14 changes: 7 additions & 7 deletions mss/BIU.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
#include "sparta/collection/Collectable.hpp"
#include "sparta/events/StartupEvent.hpp"

#include "Inst.hpp"
#include "MemoryAccessInfo.hpp"
#include "CoreTypes.hpp"
#include "FlushManager.hpp"

Expand Down Expand Up @@ -56,7 +56,7 @@ namespace olympia_mss
// Input Ports
////////////////////////////////////////////////////////////////////////////////

sparta::DataInPort<olympia::InstQueue::value_type> in_biu_req_
sparta::DataInPort<olympia::MemoryAccessInfoPtr> in_biu_req_
{&unit_port_set_, "in_biu_req", 1};

sparta::SyncInPort<bool> in_mss_ack_sync_
Expand All @@ -70,18 +70,18 @@ namespace olympia_mss
sparta::DataOutPort<uint32_t> out_biu_ack_
{&unit_port_set_, "out_biu_ack"};

sparta::DataOutPort<olympia::InstPtr> out_biu_resp_
sparta::DataOutPort<olympia::MemoryAccessInfoPtr> out_biu_resp_
{&unit_port_set_, "out_biu_resp"};

sparta::SyncOutPort<olympia::InstPtr> out_mss_req_sync_
sparta::SyncOutPort<olympia::MemoryAccessInfoPtr> out_mss_req_sync_
{&unit_port_set_, "out_mss_req_sync", getClock()};


////////////////////////////////////////////////////////////////////////////////
// Internal States
////////////////////////////////////////////////////////////////////////////////

using BusRequestQueue = std::list<olympia::InstPtr>;
using BusRequestQueue = std::list<olympia::MemoryAccessInfoPtr>;
BusRequestQueue biu_req_queue_;

const uint32_t biu_req_queue_size_;
Expand Down Expand Up @@ -112,7 +112,7 @@ namespace olympia_mss
////////////////////////////////////////////////////////////////////////////////

// Receive new BIU request from L2Cache
void receiveReqFromL2Cache_(const olympia::InstPtr &);
void receiveReqFromL2Cache_(const olympia::MemoryAccessInfoPtr &);

// Handle BIU request
void handle_BIU_Req_();
Expand All @@ -135,6 +135,6 @@ namespace olympia_mss
////////////////////////////////////////////////////////////////////////////////

// Append BIU request queue
void appendReqQueue_(const olympia::InstPtr &);
void appendReqQueue_(const olympia::MemoryAccessInfoPtr &);
};
}
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