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Registerevent for lsu_req and l2_resp
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@h0lyalg0rithm
h0lyalg0rithm committed May 17, 2024
1 parent f9a58ed commit a4cbdf4
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Showing 3 changed files with 41 additions and 62 deletions.
64 changes: 19 additions & 45 deletions core/DCache.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26,10 +26,8 @@ namespace olympia
in_l2cache_ack_.registerConsumerHandler(
CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveAckFromL2Cache_, uint32_t));

in_lsu_lookup_req_.registerConsumerEvent(in_l2_cache_resp_receive_event_);
in_l2cache_resp_.registerConsumerEvent(in_l2_cache_resp_receive_event_);
in_lsu_lookup_req_.registerConsumerEvent(in_lsu_lookup_req_receive_event_);

in_l2_cache_resp_receive_event_ >> in_lsu_lookup_req_receive_event_;
setupL1Cache_(p);

// Pipeline config
Expand Down Expand Up @@ -116,6 +114,7 @@ namespace olympia
// The lookup stage
void DCache::handleLookup_()
{
ILOG("Lookup stage");
const auto stage_id = static_cast<uint32_t>(PipelineStage::LOOKUP);
const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id];
ILOG(mem_access_info_ptr << " in Lookup stage");
Expand Down Expand Up @@ -148,19 +147,13 @@ namespace olympia

if (!mshr_itb.isValid())
{
// mshrLookup_(mem_access_info_ptr);
if (!mem_access_info_ptr->getMSHRInfoIterator().isValid())
{
ILOG("Creating new MSHR Entry " << mem_access_info_ptr);
allocateMSHREntry_(mem_access_info_ptr);
}
}

replyLSU_(mem_access_info_ptr);
}

void DCache::replyLSU_(const MemoryAccessInfoPtr & mem_access_info_ptr)
{
const auto & mshr_it = mem_access_info_ptr->getMSHRInfoIterator();
const uint64_t block_addr = getBlockAddr(mem_access_info_ptr);
const bool data_arrived = (*mshr_it)->isDataArrived();
Expand All @@ -174,23 +167,20 @@ namespace olympia
(*mshr_it)->setModified(true);
(*mshr_it)->setMemRequest(mem_access_info_ptr);
mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT);
out_lsu_lookup_ack_.send(mem_access_info_ptr);
return;
}

if (data_arrived)
else if (data_arrived)
{
ILOG("Hit on Line fill buffer (LD), block address:0x" << std::hex << block_addr);
mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT);
out_lsu_lookup_ack_.send(mem_access_info_ptr);
return;
}

// Enqueue Load in LMQ
ILOG("Load miss inst to LMQ; block address:0x" << std::hex << block_addr);
(*mshr_it)->setMemRequest(mem_access_info_ptr);
mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS);
out_lsu_lookup_req_.send(mem_access_info_ptr);
else
{
// Enqueue Load in LMQ
ILOG("Load miss inst to LMQ; block address:0x" << std::hex << block_addr);
(*mshr_it)->setMemRequest(mem_access_info_ptr);
mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS);
}
out_lsu_lookup_ack_.send(mem_access_info_ptr);
}

uint64_t DCache::getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const
Expand All @@ -203,6 +193,7 @@ namespace olympia
// Data read stage
void DCache::handleDataRead_()
{
ILOG("Data Read stage");
const auto stage_id = static_cast<uint32_t>(PipelineStage::DATA_READ);
const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id];
ILOG(mem_access_info_ptr << " in read stage");
Expand Down Expand Up @@ -233,6 +224,7 @@ namespace olympia

void DCache::mshrRequest_()
{
ILOG("Send mshr req");
if (!l2cache_busy_)
{
auto iter = mshr_file_.begin();
Expand All @@ -258,6 +250,7 @@ namespace olympia

void DCache::handleDeallocate_()
{
ILOG("Data Dellocate stage");
const auto stage_id = static_cast<uint32_t>(PipelineStage::DEALLOCATE);
const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id];
ILOG(mem_access_info_ptr << " in deallocate stage");
Expand All @@ -279,33 +272,20 @@ namespace olympia

void DCache::receiveMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr)
{
ILOG("Got memory access request from LSU " << memory_access_info_ptr);
if (!cache_refill_selected_)
{
ILOG("Cache refill was selected ignoring " << memory_access_info_ptr);
memory_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::RELOAD);
out_lsu_lookup_ack_.send(memory_access_info_ptr);
return;
}
ILOG("Adding to pipeline " << memory_access_info_ptr);
cache_pipeline_.append(memory_access_info_ptr);
ILOG("Received memory access request from LSU " << memory_access_info_ptr);
out_lsu_lookup_ack_.send(memory_access_info_ptr);
uev_free_pipeline_.schedule(1);

uev_mshr_request_.schedule(1);
in_l2_cache_resp_receive_event_.schedule();
pending_mem_access_info_ = memory_access_info_ptr;
}

void DCache::receiveRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr)
{
ILOG("Received cache refill " << memory_access_info_ptr);
// We mark the mem access to refill, this could be moved to the lower level caches later
memory_access_info_ptr->setIsRefill(true);
pending_mem_access_info_ = memory_access_info_ptr;
l2cache_busy_ = false;
cache_pipeline_.append(memory_access_info_ptr);
cache_refill_selected_ = false;
uev_free_pipeline_.schedule(1);

uev_mshr_request_.schedule(1);
in_l2_cache_resp_receive_event_.schedule();
}

void DCache::receiveAckFromL2Cache_(const uint32_t & ack)
Expand All @@ -318,12 +298,6 @@ namespace olympia
dcache_l2cache_credits_ = ack;
}

void DCache::freePipelineAppend_()
{
ILOG("Pipeline is freed");
cache_refill_selected_ = true;
}

// MSHR Entry allocation in case of miss
void DCache::allocateMSHREntry_(const MemoryAccessInfoPtr & mem_access_info_ptr)
{
Expand Down
37 changes: 21 additions & 16 deletions core/DCache.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -88,22 +88,18 @@ namespace olympia

void receiveRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr);

void freePipelineAppend_();

void mshrRequest_();

bool l2cache_busy_ = false;

bool cache_refill_selected_ = true;

// Credit bool for sending miss request to L2Cache
uint32_t dcache_l2cache_credits_ = 0;

////////////////////////////////////////////////////////////////////////////////
// Input Ports
////////////////////////////////////////////////////////////////////////////////
sparta::DataInPort<MemoryAccessInfoPtr> in_lsu_lookup_req_{&unit_port_set_,
"in_lsu_lookup_req", 0};
"in_lsu_lookup_req", 1};

sparta::DataInPort<uint32_t> in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1};

Expand All @@ -127,21 +123,31 @@ namespace olympia
////////////////////////////////////////////////////////////////////////////////
// Events
////////////////////////////////////////////////////////////////////////////////
sparta::UniqueEvent<> uev_free_pipeline_{
&unit_event_set_, "free_pipeline", CREATE_SPARTA_HANDLER(DCache, freePipelineAppend_)};

sparta::UniqueEvent<> uev_mshr_request_{
&unit_event_set_, "mshr_request", CREATE_SPARTA_HANDLER(DCache, mshrRequest_)};

void noOpEventHandler() {}

sparta::UniqueEvent<> in_l2_cache_resp_receive_event_{
&unit_event_set_, "in_l2_cache_resp_receive_event",
CREATE_SPARTA_HANDLER(DCache, noOpEventHandler)};
sparta::utils::ValidValue<MemoryAccessInfoPtr> pending_mem_access_info_;

sparta::UniqueEvent<> in_lsu_lookup_req_receive_event_{
&unit_event_set_, "in_lsu_lookup_req_receive_event",
CREATE_SPARTA_HANDLER(DCache, noOpEventHandler)};
void arbitrate_l2_lsu_req_()
{
auto flush_data = pending_mem_access_info_.getValue();
if (flush_data->isRefill())
{
ILOG("Received Refill request " << flush_data);
}
else
{
ILOG("Received LSU request " << flush_data);
}
cache_pipeline_.append(flush_data);
pending_mem_access_info_.clearValid();
uev_mshr_request_.schedule(1);
}

sparta::UniqueEvent<> in_l2_cache_resp_receive_event_{&unit_event_set_,
"in_l2_cache_resp_receive_event",
CREATE_SPARTA_HANDLER(DCache, arbitrate_l2_lsu_req_)};

////////////////////////////////////////////////////////////////////////////////
// Counters
Expand All @@ -160,7 +166,6 @@ namespace olympia
sparta::Buffer<MSHREntryInfoPtr> mshr_file_;
MSHREntryInfoAllocator & mshr_entry_allocator_;
void allocateMSHREntry_(const MemoryAccessInfoPtr & mem_access_info_ptr);
void replyLSU_(const MemoryAccessInfoPtr & mem_access_info_ptr);
};

} // namespace olympia
2 changes: 1 addition & 1 deletion test/core/lsu/Lsu_test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,7 @@ void runTest(int argc, char **argv)
cls.runSimulator(&sim, 7);
lsupipe_tester.test_inst_issue(*my_lsu, 2); // Loads operand dependency meet
cls.runSimulator(&sim, 52);
lsupipe_tester.test_replay_issue_abort(*my_lsu, 4); // Loads operand dependency meet
lsupipe_tester.test_replay_issue_abort(*my_lsu, 3); // Loads operand dependency meet
cls.runSimulator(&sim);
}

Expand Down

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