Fixed another issue related to i2f; added pipe support/debug messages (…

…#63) Couple more things: - Improved the performance of the simulator by reducing retire events - Added param support to enable/disable skipping of non-user mode instructions in an STF - Added more debug messages - Added Rename stall conditions/counters - Fixed instruction status; was not being updated
riscv-software-src · Jul 7, 2023 · 836dbbd · 836dbbd
1 parent 49b0b2b
commit 836dbbd
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diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -64,12 +64,13 @@ elseif (CMAKE_BUILD_TYPE MATCHES "^[Dd]ebug")
 elseif (CMAKE_BUILD_TYPE MATCHES "^[Pp]rofile")
   set(SPARTA_BUILD_TYPE "release")
 else()
-  message (FATAL_ERROR "Please provide a CMAKE_BUILD_TYPE: -DCMAKE_BUILD_TYPE=Release|Debug|Profile")
+  message (FATAL_ERROR "Please provide a CMAKE_BUILD_TYPE: -DCMAKE_BUILD_TYPE=Release|FastDebug|Debug|Profile")
 endif()
 
 # Profile build flags
 set(CMAKE_CXX_FLAGS_PROFILE   "-O3 -pg -g -ftime-trace")
 set(CMAKE_CXX_FLAGS_FASTDEBUG "-O3 -g")
+set(CMAKE_CXX_FLAGS_DEBUG     "-O0 -g")
 
 # Include directories
 include_directories (core mss)

diff --git a/arches/isa_json/olympia_uarch_rv64b.json b/arches/isa_json/olympia_uarch_rv64b.json
@@ -2,211 +2,211 @@
     {
         "mnemonic" : "rol",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sh2add",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "ror",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "clz",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "xnor",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sh3add",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "ctzw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sh1add.uw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "packuw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "orn",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "cpop",
         "dispatch" : ["alu"],
-        "pipe" : ["mul"],
+        "pipe" : "mul",
         "latency" : 3
     },
     {
         "mnemonic" : "rori",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "ctz",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sext.h",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "rorw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sext.b",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "slli.uw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "andn",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "add.uw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "packu",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "packw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "roriw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sh3add.uw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "pack",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sh2add.uw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "minu",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "rolw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "min",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "gorci",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "clzw",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "maxu",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "sh1add",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "max",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "grevi",
         "dispatch" : ["alu"],
-        "pipe" : ["int"],
+        "pipe" : "int",
         "latency" : 1
     },
     {
         "mnemonic" : "cpopw",
         "dispatch" : ["alu"],
-        "pipe" : ["mul"],
+        "pipe" : "mul",
         "latency" : 3
     }
 ]