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Testing fixed, cleanup and add vset wait to decode stage instead
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@aarongchan
aarongchan committed May 31, 2024
1 parent a9dd8fb commit 7840395
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Showing 56 changed files with 1,997 additions and 883 deletions.
4 changes: 2 additions & 2 deletions arches/big_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ include: medium_core.yaml

top.cpu.core0:
fetch.params.num_to_fetch: 8
decode.params.num_to_decode: 3
decode.params.num_to_decode: 8
rename.params.num_to_rename: 8
rename.params.num_integer_renames: 64
rename.params.num_float_renames: 64
Expand All @@ -34,7 +34,7 @@ top.cpu.core0.extension.core_extensions:
["float", "f2i"], # exe7
["br"], # exe8
["br"], # exe9
["vint", "vset"]
["vint", "vset", "vdiv", "vmul"]
]
# this is used to set how many units per queue
# ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
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257 changes: 242 additions & 15 deletions arches/isa_json/olympia_uarch_rv64v.json
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Original file line number Diff line number Diff line change
@@ -1,27 +1,254 @@
[
{
"mnemonic": "vadd.vv",
"pipe" : "vint",
"latency" : 1
"mnemonic": "vadd.vv",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vsub.vv",
"pipe" : "vint",
"latency" : 1
"mnemonic": "vadd.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vadd.vi",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vsub.vv",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vsetvli",
"pipe": "vset",
"latency": 1
"mnemonic": "vsub.vx",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vrsub.vi",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vrsub.vx",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vsetvli",
"pipe": "vset",
"latency": 1
},
{
"mnemonic": "vsetvl",
"pipe": "vset",
"latency": 1
},
{
"mnemonic": "vsetivli",
"pipe": "vset",
"latency": 1
},
{
"mnemonic": "vmul.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmul.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulh.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulh.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhsu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhsu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vdiv.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vdiv.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vdivu.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vdivu.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vremu.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vremu.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vrem.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vrem.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vwmul.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmul.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulsu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulsu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwaddu.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwaddu.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwaddu.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwaddu.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vsetvl",
"pipe": "vset",
"latency": 1
"mnemonic": "vsmul.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vsetivli",
"pipe": "vset",
"latency": 1
"mnemonic": "vsmul.vv",
"pipe": "vmul",
"latency": 3
}


]
40 changes: 26 additions & 14 deletions arches/medium_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,8 @@ top.cpu.core0.extension.core_extensions:
["int"], # exe2
["float", "faddsub", "fmac"], # exe3
["float", "f2i"], # exe4
["br"] # exe5
["br"], # exe5
["vint", "vset", "vdiv", "vmul"] # exe6
]

# this is used to set how many units per queue
Expand All @@ -40,24 +41,35 @@ top.cpu.core0.extension.core_extensions:
["0"], # iq0 -> exe0
["1", "2"], # iq1 -> exe1, exe2
["3", "4"], # iq2 -> exe3, exe4
["5"] # iq3 -> exe5
["5"], # iq3 -> exe5
["6"]
]

top.cpu.core0.rename.scoreboards:
# From
# |
# V
integer.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1]]
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
float.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1]]
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
vector.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
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