Add refill method to mem access info ptr

riscv-software-src · May 13, 2024 · 5d88b38 · 5d88b38
1 parent e00c124
commit 5d88b38
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Showing 3 changed files with 13 additions and 10 deletions.
diff --git a/core/DCache.cpp b/core/DCache.cpp
@@ -115,7 +115,8 @@ namespace olympia
         const auto stage_id = static_cast<uint32_t>(PipelineStage::LOOKUP);
         const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id];
         ILOG(mem_access_info_ptr << " in Lookup stage");
-        if (incoming_cache_refill_ == mem_access_info_ptr)
+        // If the mem request is a refill we dont do anything in the lookup stage
+        if (mem_access_info_ptr->isRefill())
         {
             ILOG("Incoming cache refill " << mem_access_info_ptr);
             return;
@@ -201,7 +202,7 @@ namespace olympia
         const auto stage_id = static_cast<uint32_t>(PipelineStage::DATA_READ);
         const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id];
         ILOG(mem_access_info_ptr << " in read stage");
-        if (incoming_cache_refill_ == mem_access_info_ptr)
+        if (mem_access_info_ptr->isRefill())
         {
             reloadCache_(mem_access_info_ptr->getPhyAddr());
             return;
@@ -256,10 +257,8 @@ namespace olympia
         const auto stage_id = static_cast<uint32_t>(PipelineStage::DEALLOCATE);
         const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id];
         ILOG(mem_access_info_ptr << " in deallocate stage");
-        if (incoming_cache_refill_ == mem_access_info_ptr)
+        if (mem_access_info_ptr->isRefill())
         {
-            ILOG("Refill complete " << incoming_cache_refill_);
-            incoming_cache_refill_.reset();
             const auto & mshr_it = mem_access_info_ptr->getMSHRInfoIterator();
             if (mshr_it.isValid())
             {
@@ -295,8 +294,9 @@ namespace olympia
     void DCache::receiveRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr)
     {
         ILOG("Received cache refill " << memory_access_info_ptr);
+        // We mark the mem access to refill, this could be moved to the lower level caches later
+        memory_access_info_ptr->setIsRefill(true);
         l2cache_busy_ = false;
-        incoming_cache_refill_ = memory_access_info_ptr;
         cache_pipeline_.append(memory_access_info_ptr);
         cache_refill_selected_ = false;
         uev_free_pipeline_.schedule(1);

diff --git a/core/DCache.hpp b/core/DCache.hpp
@@ -57,10 +57,6 @@ namespace olympia
 
         uint64_t getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const;
 
-        // To arbitrate between incoming request from LSU and Cache refills from BIU
-        //        bool incoming_cache_refill_ = false;
-        MemoryAccessInfoPtr incoming_cache_refill_ = nullptr;
-
         using MSHREntryInfoPtr = sparta::SpartaSharedPointer<MSHREntryInfo>;
         using MSHREntryIterator = sparta::Buffer<MSHREntryInfoPtr>::const_iterator;
         // Ongoing Refill request

diff --git a/core/MemoryAccessInfo.hpp b/core/MemoryAccessInfo.hpp
@@ -80,6 +80,7 @@ namespace olympia
             // Construct the State object here
             cache_access_state_(CacheState::NO_ACCESS),
             cache_data_ready_(false),
+            is_refill_(false),
             src_(ArchUnit::NO_ACCESS),
             dest_(ArchUnit::NO_ACCESS)
         {
@@ -141,6 +142,10 @@ namespace olympia
 
         const LoadStoreInstIterator getIssueQueueIterator() const { return issue_queue_iterator_; }
 
+        bool isRefill() const { return is_refill_; }
+
+        void setIsRefill(bool is_refill) { is_refill_ = is_refill; }
+
         void setIssueQueueIterator(const LoadStoreInstIterator & iter)
         {
             issue_queue_iterator_ = iter;
@@ -180,6 +185,8 @@ namespace olympia
         CacheState cache_access_state_;
 
         bool cache_data_ready_;
+
+        bool is_refill_;
         // Src and destination unit name for the packet
         ArchUnit src_ = ArchUnit::NO_ACCESS;
         ArchUnit dest_ = ArchUnit::NO_ACCESS;