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@h0lyalg0rithm
h0lyalg0rithm committed May 13, 2024
1 parent efe66cc commit 1975315
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Showing 3 changed files with 25 additions and 44 deletions.
45 changes: 14 additions & 31 deletions core/DCache.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,19 +12,19 @@ namespace olympia
cache_line_size_(p->l1_line_size),
num_mshr_entries_(p->mshr_entries),
mshr_file_("mshr_file", p->mshr_entries, getClock()),
mshr_entry_allocator(
mshr_entry_allocator_(
sparta::notNull(OlympiaAllocators::getOlympiaAllocators(n))->mshr_entry_allocator)
{
sparta_assert(num_mshr_entries_ > 0, "There must be atleast 1 MSHR entry");

in_lsu_lookup_req_.registerConsumerHandler(
CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getMemReqFromLSU_, MemoryAccessInfoPtr));
CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveMemReqFromLSU_, MemoryAccessInfoPtr));

in_l2cache_ack_.registerConsumerHandler(
CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getAckFromL2Cache_, uint32_t));
CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveAckFromL2Cache_, uint32_t));

in_l2cache_resp_.registerConsumerHandler(
CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, MemoryAccessInfoPtr));
CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveRespFromL2Cache_, MemoryAccessInfoPtr));

setupL1Cache_(p);

Expand Down Expand Up @@ -151,14 +151,14 @@ namespace olympia
}
}

replyLSU(mem_access_info_ptr);
replyLSU_(mem_access_info_ptr);
}

void DCache::replyLSU(const MemoryAccessInfoPtr & mem_access_info_ptr)
void DCache::replyLSU_(const MemoryAccessInfoPtr & mem_access_info_ptr)
{
const auto & mshr_it = mem_access_info_ptr->getMSHRInfoIterator();
const uint64_t block_addr = getBlockAddr(mem_access_info_ptr);
const bool data_arrived = (*mshr_it)->getDataArrived();
const bool data_arrived = (*mshr_it)->isDataArrived();
const bool is_store_inst = mem_access_info_ptr->getInstPtr()->isStoreInst();

// All ST are considered Hit
Expand Down Expand Up @@ -188,7 +188,7 @@ namespace olympia
out_lsu_lookup_req_.send(mem_access_info_ptr);
}

uint64_t DCache::getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr)
uint64_t DCache::getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const
{
const InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr();
const auto & inst_target_addr = inst_ptr->getRAdr();
Expand Down Expand Up @@ -238,7 +238,7 @@ namespace olympia
{
const auto & mshr_entry = *iter;
auto mem_info = mshr_entry->getMemRequest();
if (mshr_entry->isValid() && !mshr_entry->getDataArrived() && mem_info)
if (mshr_entry->isValid() && !mshr_entry->isDataArrived() && mem_info)
{
ILOG("Sending mshr request when not busy " << mem_info);
out_l2cache_req_.send(mem_info);
Expand Down Expand Up @@ -274,14 +274,14 @@ namespace olympia
ILOG("Deallocating pipeline for " << mem_access_info_ptr);
}

void DCache::getMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr)
void DCache::receiveMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr)
{

ILOG("Got memory access request from LSU " << memory_access_info_ptr);
if (!cache_refill_selected_)
{
ILOG("Arbitration from refill " << memory_access_info_ptr);
memory_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS);
memory_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::RELOAD);
out_lsu_lookup_ack_.send(memory_access_info_ptr);
return;
}
Expand All @@ -292,7 +292,7 @@ namespace olympia
uev_mshr_request_.schedule(1);
}

void DCache::getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr)
void DCache::receiveRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr)
{
ILOG("Received cache refill " << memory_access_info_ptr);
l2cache_busy_ = false;
Expand All @@ -304,7 +304,7 @@ namespace olympia
uev_mshr_request_.schedule(1);
}

void DCache::getAckFromL2Cache_(const uint32_t & ack)
void DCache::receiveAckFromL2Cache_(const uint32_t & ack)
{
// When DCache sends the request to L2Cache for a miss,
// This bool will be set to false, and Dcache should wait for ack from
Expand All @@ -320,30 +320,13 @@ namespace olympia
cache_refill_selected_ = true;
}

// MSHR File Lookup
void DCache::mshrLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr)
{
// const uint64_t block_address = getBlockAddr(mem_access_info_ptr);
// for (auto it = mshr_file_.begin(); it < mshr_file_.end(); it++)
// {
// auto mshr_block_addr = (*it)->getBlockAddress();
// if (mshr_block_addr == block_address)
// {
// // Address match
// mem_access_info_ptr->setMSHREntryInfoIterator(it);
// break;
// }
// }
}

// MSHR Entry allocation in case of miss
void DCache::allocateMSHREntry_(const MemoryAccessInfoPtr & mem_access_info_ptr)
{
sparta_assert(mshr_file_.size() <= num_mshr_entries_, "Appending mshr causes overflows!");

MSHREntryInfoPtr mshr_entry = sparta::allocate_sparta_shared_pointer<MSHREntryInfo>(
mshr_entry_allocator, cache_line_size_, getClock());

mshr_entry_allocator_, cache_line_size_, getClock());

const auto & it = mshr_file_.push_back(mshr_entry);
mem_access_info_ptr->setMSHREntryInfoIterator(it);
Expand Down
16 changes: 7 additions & 9 deletions core/DCache.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ namespace olympia

private:
////////////////////////////////////////////////////////////////////////////////
// L1 Cache Handling
// L1 Data Cache Handling
////////////////////////////////////////////////////////////////////////////////
using L1Handle = CacheFuncModel::Handle;
L1Handle l1_cache_;
Expand All @@ -55,7 +55,7 @@ namespace olympia

void reloadCache_(uint64_t phy_addr);

uint64_t getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr);
uint64_t getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const;

// To arbitrate between incoming request from LSU and Cache refills from BIU
// bool incoming_cache_refill_ = false;
Expand Down Expand Up @@ -86,11 +86,11 @@ namespace olympia
// Handle requests
////////////////////////////////////////////////////////////////////////////////

void getMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr);
void receiveMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr);

void getAckFromL2Cache_(const uint32_t & ack);
void receiveAckFromL2Cache_(const uint32_t & ack);

void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr);
void receiveRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr);

void freePipelineAppend_();

Expand Down Expand Up @@ -146,12 +146,10 @@ namespace olympia
"Number of DL1 cache misses",
sparta::Counter::COUNT_NORMAL};


sparta::Buffer<MSHREntryInfoPtr> mshr_file_;
MSHREntryInfoAllocator & mshr_entry_allocator;
MSHREntryInfoAllocator & mshr_entry_allocator_;
void allocateMSHREntry_(const MemoryAccessInfoPtr & mem_access_info_ptr);
void mshrLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr);
void replyLSU(const MemoryAccessInfoPtr & mem_access_info_ptr);
void replyLSU_(const MemoryAccessInfoPtr & mem_access_info_ptr);
};

} // namespace olympia
8 changes: 4 additions & 4 deletions core/MSHREntryInfo.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,18 +27,18 @@ namespace olympia

void setDataArrived(bool v) { data_arrived_ = v; }

bool getDataArrived() { return data_arrived_; }
bool isDataArrived() { return data_arrived_; }

void setMemRequest(const MemoryAccessInfoPtr & new_memory_access_info)
{
memory_access_info = new_memory_access_info;
memory_access_info_ = new_memory_access_info;
}

MemoryAccessInfoPtr & getMemRequest() { return memory_access_info; }
MemoryAccessInfoPtr & getMemRequest() { return memory_access_info_; }

private:
SimpleCacheLine line_fill_buffer_;
MemoryAccessInfoPtr memory_access_info;
MemoryAccessInfoPtr memory_access_info_;
bool data_arrived_ = false;
};
} // namespace olympia

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