Add yaml file for CI, other fixes #105
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-Add test-1.yml for CI
-Add hardcoded register testcases to dataset.cgf and rv32im.cgf (missing coverage in the division testcases riscv-non-isa/riscv-arch-test#306)
-Update in generator.py- The missing coverage of hard coded register testcases will be taken care of only if a hard coded register is assigned in the op_comb node of a coverpoint of an instruction.
-Add 'warning' as a verbose level in main.py
-Update 'opcode' to 'mnemonics' in the cgf files
-Define rs1_val_data for c.ldsp in imc.yaml
-Define rs1_val_data and rs2_val_data for instructions from zicfiss.cgf in template.yaml