Add coverpoint rd == x0 != rs

riscv-software-src · Jul 23, 2023 · c36f5bd · c36f5bd
1 parent 61a1667
commit c36f5bd
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf
@@ -225,7 +225,7 @@ datasets:
     'rs2 == rd != rs1': 0
     'rs1 == rs2 == rd': 0
     "rs1 == 'x0' != rd": 0
-    "rd == 'x0' != rs1": 0
+    "rd == 'x0' != rs1 and rs2 != 'x0'": 0
     'rs1 != rs2  and rs1 != rd and rs2 != rd': 0
 
   r4fmt_op_comb: &r4fmt_op_comb