Merge branch 'Z_inx' of https://github.com/anuani21/riscv-ctg into Z_inx

riscv-software-src · Jul 22, 2024 · 19ab1b5 · 19ab1b5
2 parents a9b88b7 + b03cbd6
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -2,10 +2,15 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+
 Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch.
 Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
 versioned header while the `WIP-DEV` is left empty
 
+## [0.12.2] - 2024-03-06
+- Add Zfa support. (PR#60)
+- Initial covergroups for Zvk* instructions (PR#61)
+
 ## [0.12.1] - 2024-02-27
 - Fix test.yml
 

diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py
@@ -4,4 +4,4 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = '[email protected]'
-__version__ = '0.12.1'
+__version__ = '0.12.2'