Update intro.adoc

Co-authored-by: Paul Donahue <[email protected]>
Signed-off-by: Aote Jin <[email protected]>

intro.adoc

@@ -12,7 +12,7 @@ A summary of the changes introduced by _The RISC-V External Debug Security Speci
     - *Non-secure debug:* Add a non-secure debug state to relax security constraints.
     - *Debug Mode entry:* External debugger can only halt the hart and enter debug mode when debug is allowed in current privilege mode; all operations are executed with <<dbgaccpriv, debug access privilege>> instead of M-mode privilege.
     - *Memory Access:* Memory access from a hart’s point of view using the Program Buffer or an Abstract Command must be checked by the hart's memory protection mechanisms as if the hart is running at <<dbgaccpriv, debug access privilege>>; memory access from the Debug Module using System Bus Access must be checked by a system memory protection mechanism, such as IOPMP or WorldGuard.
-    - *Register Access:* Register access using Program Buffer or the Abstract Command works as if the hart is running in <<dbgaccpriv, debug access privilege>> instead of M-mode privilege. The debug CSRs (`dcsr` and `dpc` ) are shadowed in supervisor domains while Smtdeleg/Sstcfg extensions expose the trigger CSRs to supervisor domains through indirect CSR access. 
+    - *Register Access:* Register access using the Program Buffer or an Abstract Command works as if the hart is running in <<dbgaccpriv, debug access privilege>> instead of M-mode privilege. The debug CSRs (`dcsr` and `dpc` ) are shadowed in supervisor domains while Smtdeleg/Sstcfg extensions expose the trigger CSRs to supervisor domains through indirect CSR access. 
     - *Triggers:* Triggers (with action=1) can only fire or match when external debug is allowed in current privilege.
 
 === Terminology