Add support Zdinx extension

coverage/cgfs_fext/RV32Zdinx/fadd.d.cgf

@@ -0,0 +1,188 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fadd.d_b1:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b1(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b2:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b2(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b3:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b3(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b4:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b4(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b5:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b5(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b7:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b7(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b8:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b8(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b10:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b10(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b11:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b11(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b12:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b12(flen,64, "fadd.d", 2, True)': 0
+
+fadd.d_b13:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fadd.d: 0
+    rs1: 
+      <<: *pair_regs
+    rs2:
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b13(flen,64, "fadd.d", 2, True)': 0

coverage/cgfs_fext/RV32Zdinx/fclass.d.cgf

@@ -0,0 +1,14 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fclass.d_b1:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fclass.d: 0
+    rs1: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b1(flen,64, "fclass.d", 1, True)': 0

coverage/cgfs_fext/RV32Zdinx/fcvt.d.l.cgf

@@ -0,0 +1,14 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fcvt.d.l_b25:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fcvt.d.l: 0
+    rs1: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b25(flen,64, "fcvt.d.l", 1, True)': 0

coverage/cgfs_fext/RV32Zdinx/fcvt.d.lu.cgf

@@ -0,0 +1,17 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fcvt.d.lu_b25:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fcvt.d.lu: 0
+    rs1: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b25(flen,64, "fcvt.d.lu", 1, True)': 0
+
+
+

coverage/cgfs_fext/RV32Zdinx/fcvt.d.w.cgf

@@ -0,0 +1,28 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fcvt.d.w_b25:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fcvt.d.w: 0
+    rs1: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b25(flen,32, "fcvt.d.w", 1, True)': 0
+
+fcvt.d.w_b26:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx.*)
+    mnemonics: 
+      fcvt.d.w: 0
+    rs1: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b26(32, "fcvt.d.w", 1, True)': 0
+

coverage/cgfs_fext/RV32Zdinx/fcvt.d.wu.cgf

@@ -0,0 +1,28 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fcvt.d.wu_b25:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx)
+    mnemonics: 
+      fcvt.d.wu: 0
+    rs1: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b25(flen,32, "fcvt.d.wu", 1, True)': 0
+
+fcvt.d.wu_b26:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zdinx)
+    mnemonics: 
+      fcvt.d.wu: 0
+    rs1: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b26(32, "fcvt.d.wu", 1, True)': 0
+