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Draft : Added test cases for load address match trigger in sdtrig extension #487

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Draft : Added test cases for load address match trigger in sdtrig extension #487

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Commits on Sep 3, 2024

  1. Added test cases for load address match trigger in sdtrig extension

    @anuani21
    anuani21 committed Sep 3, 2024
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  2. Merge branch 'dev' into Sdtrig

    @anuani21
    anuani21 authored Sep 3, 2024
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Commits on Sep 30, 2024

  1. Updated load test cases and added store, execute test cases with diff… 

    …erent match value
    @anuani21
    anuani21 committed Sep 30, 2024
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  2. Merge branch 'dev' into Sdtrig

    @anuani21
    anuani21 authored Sep 30, 2024
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Commits on Oct 4, 2024

  1. updated tests

    @anuani21
    anuani21 committed Oct 4, 2024
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  2. Merge branch 'Sdtrig' of https://github.com/anuani21/riscv-arch-test … 

    …into Sdtrig
    @anuani21
    anuani21 committed Oct 4, 2024
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  3. Modified test cases

    @anuani21
    anuani21 committed Oct 4, 2024
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  4. Removed 

    Signed-off-by: anuani21 <[email protected]>
    @anuani21
    anuani21 authored Oct 4, 2024
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  5. Delete riscv-test-suite/rv32i_m/sdtrig/store_match5.S 

    Signed-off-by: anuani21 <[email protected]>
    @anuani21
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  6. Delete riscv-test-suite/rv32i_m/sdtrig/execute_match0.S 

    Signed-off-by: anuani21 <[email protected]>
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  7. Delete riscv-test-suite/rv32i_m/sdtrig/execute_match2.S 

    Signed-off-by: anuani21 <[email protected]>
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  8. Delete riscv-test-suite/rv32i_m/sdtrig/execute_match3.S 

    Signed-off-by: anuani21 <[email protected]>
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  9. Delete riscv-test-suite/rv32i_m/sdtrig/execute_match4.S 

    Signed-off-by: anuani21 <[email protected]>
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  10. Delete riscv-test-suite/rv32i_m/sdtrig/execute_match5.S 

    Signed-off-by: anuani21 <[email protected]>
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  11. Delete riscv-test-suite/rv32i_m/sdtrig/load_match0.S 

    Signed-off-by: anuani21 <[email protected]>
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  12. Delete riscv-test-suite/rv32i_m/sdtrig/load_match1.S 

    Signed-off-by: anuani21 <[email protected]>
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  13. Delete riscv-test-suite/rv32i_m/sdtrig/load_match2.S 

    Signed-off-by: anuani21 <[email protected]>
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  14. Delete riscv-test-suite/rv32i_m/sdtrig/load_match3.S 

    Signed-off-by: anuani21 <[email protected]>
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  15. Delete riscv-test-suite/rv32i_m/sdtrig/load_match4.S 

    Signed-off-by: anuani21 <[email protected]>
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  16. Delete riscv-test-suite/rv32i_m/sdtrig/load_match5.S 

    Signed-off-by: anuani21 <[email protected]>
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  17. Delete riscv-test-suite/rv32i_m/sdtrig/store_match0.S 

    Signed-off-by: anuani21 <[email protected]>
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  18. Delete riscv-test-suite/rv32i_m/sdtrig/store_match1.S 

    Signed-off-by: anuani21 <[email protected]>
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  19. Delete riscv-test-suite/rv32i_m/sdtrig/store_match2.S 

    Signed-off-by: anuani21 <[email protected]>
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  20. Delete riscv-test-suite/rv32i_m/sdtrig/store_match3.S 

    Signed-off-by: anuani21 <[email protected]>
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  21. Delete riscv-test-suite/rv32i_m/sdtrig/store_match4.S 

    Signed-off-by: anuani21 <[email protected]>
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  22. Delete riscv-test-suite/rv32i_m/sdtrig/src directory 

    Signed-off-by: anuani21 <[email protected]>
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  23. Updated test cases for execute,load and store operations

    @anuani21
    anuani21 committed Oct 4, 2024
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Commits on Oct 15, 2024

  1. Merge branch 'riscv-non-isa:dev' into Sdtrig

    @anuani21
    anuani21 authored Oct 15, 2024
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  2. Updated test cases

    @anuani21
    anuani21 committed Oct 15, 2024
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Commits on Nov 1, 2024

  1. Icount test cases

    @anuani21
    anuani21 committed Nov 1, 2024
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  2. Merge branch 'riscv-non-isa:dev' into Sdtrig

    @anuani21
    anuani21 authored Nov 1, 2024
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