fixed RVTEST_CASE and check ISA

RVTEST_CASE contains the toolchain command. Check ISA is for selecting tests. Added Smclint to check ISA so these tests are only selected when included in the dut isa yaml.
riscv-non-isa · Aug 3, 2023 · c7c1bd1 · c7c1bd1
1 parent 831b022
commit c7c1bd1
Show file tree

Hide file tree

Showing 14 changed files with 14 additions and 14 deletions.
diff --git a/riscv-test-suite/rv32i_m/Smclint/src/direct-01.S b/riscv-test-suite/rv32i_m/Smclint/src/direct-01.S
@@ -111,7 +111,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",direct-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",direct-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/direct-02.S b/riscv-test-suite/rv32i_m/Smclint/src/direct-02.S
@@ -115,7 +115,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",direct-02)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",direct-02)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/ecall-01.S b/riscv-test-suite/rv32i_m/Smclint/src/ecall-01.S
@@ -119,7 +119,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ecall-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ecall-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-01.S b/riscv-test-suite/rv32i_m/Smclint/src/level-01.S
@@ -106,7 +106,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-02.S b/riscv-test-suite/rv32i_m/Smclint/src/level-02.S
@@ -108,7 +108,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-02)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-02)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-03.S b/riscv-test-suite/rv32i_m/Smclint/src/level-03.S
@@ -111,7 +111,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-03)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-03)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/level-04.S b/riscv-test-suite/rv32i_m/Smclint/src/level-04.S
@@ -111,7 +111,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-04)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",level-04)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/msw-01.S b/riscv-test-suite/rv32i_m/Smclint/src/msw-01.S
@@ -108,7 +108,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",msw-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",msw-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/mtimer-01.S b/riscv-test-suite/rv32i_m/Smclint/src/mtimer-01.S
@@ -105,7 +105,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",mtimer-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",mtimer-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/nomint-01.S b/riscv-test-suite/rv32i_m/Smclint/src/nomint-01.S
@@ -102,7 +102,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",nomint-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",nomint-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/nomint-02.S b/riscv-test-suite/rv32i_m/Smclint/src/nomint-02.S
@@ -102,7 +102,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",nomint-02)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",nomint-02)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/vectored-01.S b/riscv-test-suite/rv32i_m/Smclint/src/vectored-01.S
@@ -114,7 +114,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",vectored-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",vectored-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/vectored-02.S b/riscv-test-suite/rv32i_m/Smclint/src/vectored-02.S
@@ -118,7 +118,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",vectored-02)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",vectored-02)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE

diff --git a/riscv-test-suite/rv32i_m/Smclint/src/wfi-01.S b/riscv-test-suite/rv32i_m/Smclint/src/wfi-01.S
@@ -104,7 +104,7 @@ RVTEST_CODE_BEGIN
 RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",wfi-01)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Smclint.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",wfi-01)
     # ---------------------------------------------------------------------------------------------
     LA(     t0,first_mtvec_handler)
     ori t0, t0, RVMODEL_MTVEC_MODE