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Added Covergroups and updated tests
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@MuhammadHammad001
MuhammadHammad001 committed Sep 17, 2024
1 parent f70c27c commit a9b8c6c
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Showing 33 changed files with 1,230 additions and 286 deletions.
640 changes: 640 additions & 0 deletions coverage/pmm.cgf
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag00.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag00)

RVTEST_SIGBASE( x13,signature_x13_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag01.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag01)

RVTEST_SIGBASE( x13,signature_x13_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag10.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag02)

RVTEST_SIGBASE( x13,signature_x13_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_S_sv48_tag11.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV48_tag03)

RVTEST_SIGBASE( x13,signature_x13_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag00.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag00)

RVTEST_SIGBASE( x13,signature_x13_1)

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4 changes: 2 additions & 2 deletions riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag01.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag01)

RVTEST_SIGBASE( x13,signature_x13_1)

Expand Down Expand Up @@ -117,7 +117,7 @@ satp_setup:

# -------------------- Enter and Exit M Mode ----------------------------------

RVTEST_GOTO_LOWER_MODE Smode // Go back to Supervisor mode
RVTEST_GOTO_LOWER_MODE Umode // Go back to Supervisor mode

# -------------------- Test PMM (Pointer Masking) without Masking --------------

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag10.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag02)

RVTEST_SIGBASE( x13,signature_x13_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_U_sv48_tag11.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_U_mode_SV48_tag03)

RVTEST_SIGBASE( x13,signature_x13_1)

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52 changes: 24 additions & 28 deletions riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag00.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_S_mode_SV48_tag00)

RVTEST_SIGBASE( x13,signature_x13_1)

Expand All @@ -36,7 +36,7 @@ main:
# --------------------------- Define Addresses -------------------------------
.set pa_rvtest_code_begin, 0x8000000000039c // 56-bit physical address of the code section
.set pa_rvtest_data_begin, 0x80000000003530 // 56-bit physical address of the data section
.set pa_rvtest_sig_begin, 0x80000000006218 // 56-bit physical address of the signature section
.set pa_rvtest_sig_begin, 0x80000000006218 // 56-bit physical address of the signature section
.set va_rvtest_code_begin, 0xFFFF80000000039c // 48-bit virtual address of the code section
.set va_rvtest_data_begin, 0x0000500000000000 // 48-bit virtual address of the data section
.set va_rvtest_sig_begin, 0x0000500000006218 // 48-bit virtual address of the signature section
Expand Down Expand Up @@ -124,30 +124,28 @@ satp_setup:
vm_en:
LI (x8, va_rvtest_data_begin)
nop
LREG x9, 0(x8) // test the load access
nop
SREG x9, 0(x8) // test the store access
nop
lb x9, 0(x8) // test the load access
nop
sb x9, 0(x8) // test the store access
nop
lh x9, 0(x8) // test the load access
nop
sh x9, 0(x8) // test the store access
lw x9, 0(x8) // test the load access
nop
ld x9, 0(x8) // test the load access
nop
sd x9, 0(x8) // test the store access
sb x9, 0(x8) // test the store access
nop
lbu x9, 0(x8) // test the load access
sh x9, 0(x8) // test the store access
nop
lhu x9, 0(x8) // test the load access
sw x9, 0(x8) // test the store access
nop
lwu x9, 0(x8)
sd x9, 0(x8) // test the store access
nop

# -------------------- Disable Virtualization ---------------------------------
# lbu x9, 0(x8) // test the load access
# nop
# lhu x9, 0(x8) // test the load access
# nop
# lwu x9, 0(x8)
nop# -------------------- Disable Virtualization ---------------------------------

RVTEST_GOTO_MMODE // Switch back to Machine mode

Expand All @@ -167,30 +165,28 @@ vm_en:
vm_en_with_pointer_masking:
LI (x8, va_rvtest_data_begin)
nop
LREG x9, 0(x8) // test the load access
nop
SREG x9, 0(x8) // test the store access
nop
lb x9, 0(x8) // test the load access
nop
sb x9, 0(x8) // test the store access
nop
lh x9, 0(x8) // test the load access
nop
sh x9, 0(x8) // test the store access
lw x9, 0(x8) // test the load access
nop
ld x9, 0(x8) // test the load access
nop
sd x9, 0(x8) // test the store access
sb x9, 0(x8) // test the store access
nop
lbu x9, 0(x8) // test the load access
sh x9, 0(x8) // test the store access
nop
lhu x9, 0(x8) // test the load access
sw x9, 0(x8) // test the store access
nop
lwu x9, 0(x8)
sd x9, 0(x8) // test the store access
nop

# -------------------- Disable Virtualization ---------------------------------
# lbu x9, 0(x8) // test the load access
# nop
# lhu x9, 0(x8) // test the load access
# nop
# lwu x9, 0(x8)
nop# -------------------- Disable Virtualization ---------------------------------

RVTEST_GOTO_MMODE // Switch back to Machine mode

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49 changes: 23 additions & 26 deletions riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag01.S
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_S_mode_SV48_tag01)

RVTEST_SIGBASE( x13,signature_x13_1)

Expand Down Expand Up @@ -124,29 +124,28 @@ satp_setup:
vm_en:
LI (x8, va_rvtest_data_begin)
nop
LREG x9, 0(x8) // test the load access
nop
SREG x9, 0(x8) // test the store access
nop
lb x9, 0(x8) // test the load access
nop
sb x9, 0(x8) // test the store access
nop
lh x9, 0(x8) // test the load access
nop
sh x9, 0(x8) // test the store access
lw x9, 0(x8) // test the load access
nop
ld x9, 0(x8) // test the load access
nop
sd x9, 0(x8) // test the store access
sb x9, 0(x8) // test the store access
nop
lbu x9, 0(x8) // test the load access
sh x9, 0(x8) // test the store access
nop
lhu x9, 0(x8) // test the load access
sw x9, 0(x8) // test the store access
nop
lwu x9, 0(x8)
sd x9, 0(x8) // test the store access
nop
# lbu x9, 0(x8) // test the load access
# nop
# lhu x9, 0(x8) // test the load access
# nop
# lwu x9, 0(x8)
nop

# -------------------- Disable Virtualization ---------------------------------

RVTEST_GOTO_MMODE // Switch back to Machine mode
Expand All @@ -167,30 +166,28 @@ vm_en:
vm_en_with_pointer_masking:
LI (x8, va_rvtest_data_begin)
nop
LREG x9, 0(x8) // test the load access
nop
SREG x9, 0(x8) // test the store access
nop
lb x9, 0(x8) // test the load access
nop
sb x9, 0(x8) // test the store access
nop
lh x9, 0(x8) // test the load access
nop
sh x9, 0(x8) // test the store access
lw x9, 0(x8) // test the load access
nop
ld x9, 0(x8) // test the load access
nop
sd x9, 0(x8) // test the store access
sb x9, 0(x8) // test the store access
nop
lbu x9, 0(x8) // test the load access
sh x9, 0(x8) // test the store access
nop
lhu x9, 0(x8) // test the load access
sw x9, 0(x8) // test the store access
nop
lwu x9, 0(x8)
sd x9, 0(x8) // test the store access
nop

# -------------------- Disable Virtualization ---------------------------------
# lbu x9, 0(x8) // test the load access
# nop
# lhu x9, 0(x8) // test the load access
# nop
# lwu x9, 0(x8)
nop# -------------------- Disable Virtualization ---------------------------------

RVTEST_GOTO_MMODE // Switch back to Machine mode

Expand Down
50 changes: 23 additions & 27 deletions riscv-test-suite/rv64i_m/pmm/pmm_basic/PMM_basic_01_S_sv48_tag10.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1

RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_S_mode_SV57_tag0)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_basic_S_mode_SV48_tag02)

RVTEST_SIGBASE( x13,signature_x13_1)

Expand Down Expand Up @@ -124,30 +124,28 @@ satp_setup:
vm_en:
LI (x8, va_rvtest_data_begin)
nop
LREG x9, 0(x8) // test the load access
nop
SREG x9, 0(x8) // test the store access
nop
lb x9, 0(x8) // test the load access
nop
sb x9, 0(x8) // test the store access
nop
lh x9, 0(x8) // test the load access
nop
sh x9, 0(x8) // test the store access
lw x9, 0(x8) // test the load access
nop
ld x9, 0(x8) // test the load access
nop
sd x9, 0(x8) // test the store access
sb x9, 0(x8) // test the store access
nop
lbu x9, 0(x8) // test the load access
sh x9, 0(x8) // test the store access
nop
lhu x9, 0(x8) // test the load access
sw x9, 0(x8) // test the store access
nop
lwu x9, 0(x8)
sd x9, 0(x8) // test the store access
nop

# -------------------- Disable Virtualization ---------------------------------
# lbu x9, 0(x8) // test the load access
# nop
# lhu x9, 0(x8) // test the load access
# nop
# lwu x9, 0(x8)
nop# -------------------- Disable Virtualization ---------------------------------

RVTEST_GOTO_MMODE // Switch back to Machine mode

Expand All @@ -167,30 +165,28 @@ vm_en:
vm_en_with_pointer_masking:
LI (x8, va_rvtest_data_begin)
nop
LREG x9, 0(x8) // test the load access
nop
SREG x9, 0(x8) // test the store access
nop
lb x9, 0(x8) // test the load access
nop
sb x9, 0(x8) // test the store access
nop
lh x9, 0(x8) // test the load access
nop
sh x9, 0(x8) // test the store access
lw x9, 0(x8) // test the load access
nop
ld x9, 0(x8) // test the load access
nop
sd x9, 0(x8) // test the store access
sb x9, 0(x8) // test the store access
nop
lbu x9, 0(x8) // test the load access
sh x9, 0(x8) // test the store access
nop
lhu x9, 0(x8) // test the load access
sw x9, 0(x8) // test the store access
nop
lwu x9, 0(x8)
sd x9, 0(x8) // test the store access
nop

# -------------------- Disable Virtualization ---------------------------------
# lbu x9, 0(x8) // test the load access
# nop
# lhu x9, 0(x8) // test the load access
# nop
# lwu x9, 0(x8)
nop# -------------------- Disable Virtualization ---------------------------------

RVTEST_GOTO_MMODE // Switch back to Machine mode

Expand Down
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