Update RVTEST_ISA for fma type D instructions

riscv-non-isa · Sep 5, 2024 · 7a24bb1 · 7a24bb1
1 parent 7a306f8
commit 7a24bb1
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diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-001.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-001.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-002.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-002.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-003.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-003.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-004.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-004.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-005.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-005.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-006.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-006.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-007.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-007.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-008.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-008.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-009.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-009.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-010.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-010.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-011.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-011.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-012.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-012.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-013.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-013.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-014.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-014.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-015.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-015.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-016.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-016.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-017.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-017.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-018.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-018.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-019.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-019.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-020.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-020.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-021.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-021.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-022.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-022.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-023.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-023.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-024.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-024.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-025.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-025.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-026.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-026.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-027.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-027.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-028.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-028.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-029.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-029.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-030.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-030.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-031.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-031.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-032.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-032.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-033.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-033.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-034.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-034.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-035.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-035.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-036.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-036.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-037.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-037.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-038.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-038.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-039.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-039.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-040.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-040.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-041.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-041.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-042.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-042.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-043.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-043.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-044.S b/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-044.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")
+RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr,RV32EFD_Zicsr,RV64EFD_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point