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Keep using some import * and variables in ctg and isca to support `…
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…eval()` working correctly

Signed-off-by: MingZhu Yan <[email protected]>
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trdthg committed Nov 1, 2024
1 parent 8b80ca2 commit 62aea46
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Showing 3 changed files with 7 additions and 2 deletions.
1 change: 1 addition & 0 deletions riscv-ctg/riscv_ctg/constants.py
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Expand Up @@ -2,6 +2,7 @@

import os
from math import sqrt
from math import * # noqa: F403
from string import Template

root = os.path.abspath(os.path.dirname(__file__))
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6 changes: 4 additions & 2 deletions riscv-ctg/riscv_ctg/generator.py
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Expand Up @@ -4,9 +4,11 @@
from constraint import Problem, MinConflictsSolver, AllDifferentConstraint
import re
from riscv_ctg.constants import twos, e_regset, signode_template, case_template, part_template, test_template, default_regset
from riscv_ctg.constants import * # noqa: F403
from riscv_ctg.log import logger
from riscv_ctg.helpers import nan_box, sgn_extd, merge_fields_f, ExtractException
from riscv_ctg.dsp_function import gen_pair_reg_data, concat_simd_data
from riscv_ctg.dsp_function import * # noqa: F403
from riscv_isac.InstructionObject import instructionObject
import struct
import sys
Expand Down Expand Up @@ -1010,7 +1012,7 @@ def valreg(self,instr_dict):
else:
FLEN = 0
XLEN = max(self.opnode['xlen'])
_SIGALIGN = max(XLEN,FLEN)/8
SIGALIGN = max(XLEN,FLEN)/8 # noqa: F841
stride_sz = eval(suffix)
template = Template(eval(self.opnode['val']['val_template']))
width = self.iflen if self.is_fext else self.flen
Expand Down Expand Up @@ -1135,7 +1137,7 @@ def swreg(self, instr_dict):
else:
FLEN = 0
XLEN = max(self.opnode['xlen'])
_SIGALIGN = max(XLEN,FLEN)/8
SIGALIGN = max(XLEN,FLEN)/8 # noqa: F841
stride_sz = eval(suffix)
for instr in instr_dict:
if 'rs1' in instr and instr['rs1'] in available_reg:
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2 changes: 2 additions & 0 deletions riscv-isac/riscv_isac/cgf_normalize.py
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@@ -1,9 +1,11 @@
# See LICENSE.incore for details
from math import ceil, sqrt
from math import * # noqa: F403
import riscv_isac.utils as utils
import itertools
import random
from riscv_isac.fp_dataset import logger
from riscv_isac.fp_dataset import * # noqa: F403


def twos(val,bits):
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