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Updated PMP Tests
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@UmerShahidengr
UmerShahidengr committed Oct 27, 2023
1 parent 8890fd6 commit 5e8a42c
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25 changes: 8 additions & 17 deletions riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CFG-reg.S
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Expand Up @@ -27,7 +27,7 @@
*/
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand All @@ -43,7 +43,6 @@ RVTEST_SIGBASE( x3,signature_x3_1)
.attribute stack_align, 16
.align 2
.option norvc
//#define OFFSET 4 // In case of RV32
#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP)
#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP)
main:
Expand All @@ -54,38 +53,34 @@ main:
// Loop to SET ALL pmpcfg REGs to zero
.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
.rept 4 // START OF LOOP
csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value)
csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value)
.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
.endr // END OF LOOP BODY
// Loop to SET ALL pmpaddr REGs to zero
.set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0
.rept 16 // START OF LOOP
csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value)
csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value)
.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
.endr // END OF LOOP BODY

//////////////////// Locked bit TEST 1 /////////////////////////////////////////////
.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
.set OFFSET, 0
.rept 4 // START OF LOOP
csrw pmpcfgi, a5 // WRITE pmpcfgi with ALL 1s, Locked the lock-bit [7,15,23,31]
nop // Added nop in case of trap
csrr a4, pmpcfgi // READ pmpcfgi
// THIS READ WILL ALSO CONFIRM THE ZERO BITs OF PMPCFGi REG.
// BIT 5-6, BIT 13-14, BIT 21-22, BIT 29-30 must be hardwired to zero
// Verify that LOCKED bits are HIGH, and ZERO bits are zero
RVTEST_SIGUPD(x3,a4, OFFSET)
.set OFFSET, OFFSET+REGWIDTH // Added offset in x9
RVTEST_SIGUPD(x3,a4)
// TRY TO WRITE CFG REGISTER AGAIN (TRAP in case of LOCKED bit is HIGH)
csrw pmpcfgi, x5 // WRITE pmpcfgi with some other values
nop // Added nop in case of trap
csrr a4, pmpcfgi // READ pmpcfgi
// Since Locked bit is high, so this should return the old value!!!
RVTEST_SIGUPD(x3,a4,OFFSET)
.set OFFSET, OFFSET+REGWIDTH // Added offset in x9
RVTEST_SIGUPD(x3,a4)


.set pmpaddri, pmpcfgi+(PMPADDR0-PMPCFG0)+(pmpcfgi-PMPCFG0)
.set pmpaddri, PMPADDR0+4*(pmpcfgi-PMPCFG0)
// Initialize an iterating variable with the address of pmpaddr0 in 1st iteration (when pmpcfgi=pmpcfg0)
// Initialize an iterating variable with the address of pmpaddr4 in 2nd iteration (when pmpcfgi=pmpcfg1)
// Initialize an iterating variable with the address of pmpaddr8 in 3rd iteration (when pmpcfgi=pmpcfg2)
Expand All @@ -97,19 +92,15 @@ main:
nop // Added nop in case of trap
csrr a4, pmpaddri // READ pmpaddr0, value should not have been changed
nop // Added nop in case of trap
RVTEST_SIGUPD(x3,a4, OFFSET)
.set OFFSET, OFFSET+REGWIDTH // Added offset in x9
RVTEST_SIGUPD(x3,a4)
.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
.endr // END OF INNER LOOP BODY

.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
.endr // END OF OUTER LOOP BODY

#endif

# ---------------------------------------------------------------------------------------------
# HALT

RVTEST_CODE_END
RVMODEL_HALT

Expand Down Expand Up @@ -152,4 +143,4 @@ gpr_save:
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
RVMODEL_DATA_END
11 changes: 5 additions & 6 deletions riscv-test-suite/rv32i_m/privilege/pmp32/PMP-CSR-access.S
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Expand Up @@ -17,7 +17,7 @@
#define rvtest_strap_routine
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand All @@ -41,13 +41,13 @@ main:
// Loop to SET ALL pmpcfg REGs to zero
.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
.rept 4 // START OF LOOP
csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value)
csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value)
.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
.endr // END OF LOOP BODY
// Loop to SET ALL pmpaddr REGs to zero
.set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0
.rept 16 // START OF LOOP
csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value)
csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value)
.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
.endr // END OF LOOP BODY
//////////////// VERIFICATION /////////////////////////////////////////
Expand Down Expand Up @@ -104,7 +104,6 @@ main:
nop // Added nop in case of trap
/////////////////// Switch back to M-mode ////////////////////////////////////////////
RVTEST_GOTO_MMODE

csrr a4, mstatus // VERIFICATION of M-mode
nop // Added nop in case of trap
RVTEST_SIGUPD(x13,a4)
Expand All @@ -127,11 +126,11 @@ main:
/////////////////// TEST 01 ////////////////////////////////////////////
// WRITING pmpaddr registers //////////////////////////////////////////
// Write in M-mode will be valid, Write in other modes will cause trap
csrw pmpaddr8, x2 // Write pmpaddr8 in u mode (TRAP)
csrw pmpaddr0, x2 // Write pmpaddr0 in u mode (TRAP)
nop // Added nop in case of trap
//////////////// VERIFICATION /////////////////////////////////////////
// READING pmpaddr in S-mode /////////////////////////////////////////
csrr a4, pmpaddr12 // Reading pmpaddr12 in U mode (TRAP)
csrr a4, pmpaddr0 // Reading pmpaddr0 in U mode (TRAP)
nop // Added nop in case of trap

#endif
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/PMP-NAPOT-RX.S
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Expand Up @@ -13,7 +13,7 @@
#define rvtest_strap_routine
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

# Test code region
.section .text.init
Expand Down
25 changes: 1 addition & 24 deletions riscv-test-suite/rv32i_m/privilege/pmp32/PMP-granularity.S
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Expand Up @@ -13,7 +13,7 @@
#define rvtest_strap_routine
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

# Test code region
.section .text.init
Expand All @@ -29,27 +29,6 @@ RVTEST_SIGBASE( x3,signature_x3_1)
.attribute stack_align, 16
.align 2
main:
////////////// SETTING DEFAULTS TO ZERO ///////////////////////////////////////
csrw pmpcfg0, x0
csrw pmpcfg1, x0
csrw pmpcfg2, x0
csrw pmpcfg3, x0
csrw pmpaddr0, x0
csrw pmpaddr1, x0
csrw pmpaddr2, x0
csrw pmpaddr3, x0
csrw pmpaddr4, x0
csrw pmpaddr5, x0
csrw pmpaddr6, x0
csrw pmpaddr7, x0
csrw pmpaddr8, x0
csrw pmpaddr9, x0
csrw pmpaddr10, x0
csrw pmpaddr11, x0
csrw pmpaddr12, x0
csrw pmpaddr13, x0
csrw pmpaddr14, x0
csrw pmpaddr15, x0
//////////////////// Granularity TEST 1 /////////////////////////////////////////////
detect_granule: // AS INSTRUCTED IN RISC-V Privileged Architectures V1.12-draft
// RISC-V Priv Architecture Manual (Article 3.7.1)
Expand Down Expand Up @@ -89,12 +68,10 @@ calculations:
RVTEST_SIGUPD(x3,x7)
//////////////////////// DETECT pmpaddri[G-1:0] bits must be read zero in case of pmpcfgi.A[1]==0
//////////////////////// uneffecting the underlaying actual value for G>=1

csrw pmpcfg0, 0 // WRITE 0 to pmpcfg0
nop // Added nop in case of trap
csrw pmpaddr0, a4 // WRITE ALL 1s in pmpaddr0
csrr a5, pmpaddr0 // READ the address

// DISPLAY pmpaddr0
RVTEST_SIGUPD(x3,a5)
#endif
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-R.S
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Expand Up @@ -23,7 +23,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RW.S
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Expand Up @@ -24,7 +24,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
38 changes: 27 additions & 11 deletions riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RWX.S
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Expand Up @@ -22,7 +22,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down Expand Up @@ -64,13 +64,13 @@ main:
// Loop to SET ALL pmpcfg REGs to zero
.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
.rept 4 // START OF LOOP
csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value)
csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value)
.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
.endr // END OF LOOP BODY
// Loop to SET ALL pmpaddr REGs to zero
.set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0
.rept 16 // START OF LOOP
csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value)
csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value)
.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
.endr // END OF LOOP BODY

Expand Down Expand Up @@ -106,13 +106,27 @@ main:
csrw satp, x0 // Disable Address Translation
// PMP Configuration
/* PMP is configure in the following order:
1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region.
1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled.
This region is the part of the code memory containing our code and the region between code_end to data_begin.
For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to
declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region.
2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail.)
This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2.
Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2
3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test.
This region has been declared by entering rvtest_code_end into pmpaddr3 and
RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST)

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@allenjbaum

allenjbaum Nov 15, 2023

Collaborator

This comment says you're both RETURN_INSTRUCTION and RAM_LOCATION_FOR_TEST into PMPADDR1
Also, RAM_LOCATION_FOR_TEST is configured in both PMPADDR0 and PMPADDR2
to pmpaddr3(rvtest_code_end) into TOR mode
by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT))
4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled.
This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions.
For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High)
into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)).
This PMP Region is mandatory to access signature area in S,U mode */

2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2
3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT))
4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */
/* Assigning addresses to PMP address registers */
LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0
srl x4, x4, PMP_SHIFT // Shift right by 2 times
Expand Down Expand Up @@ -157,8 +171,8 @@ main:
// VERIFICATION IN U-Mode
RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode
VERIFICATION_RWX TEST_FOR_EXECUTION
nop
j exit

RAM_LOCATION_FOR_TEST:
.fill 3*(XLEN/32),4,0x12345678
TEST_FOR_EXECUTION:
Expand All @@ -176,6 +190,8 @@ RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4



rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
Expand Down Expand Up @@ -213,4 +229,4 @@ sig_end_canary:
CANARY;
rvtest_sig_end:
PMP_region_High:
RVMODEL_DATA_END
RVMODEL_DATA_END
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-RX.S
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Expand Up @@ -22,7 +22,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NA4-X.S
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Expand Up @@ -22,7 +22,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-R.S
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Expand Up @@ -24,7 +24,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RW.S
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RWX.S
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-RX.S
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/pmp32/pmp-NAPOT-X.S
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@

#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")
# Test code region
.section .text.init
.globl rvtest_entry_point
Expand Down
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