Merge pull request #398 from davidharrishmc/master

Fixed missing check ISA fields in RVTEST_CASE for new div and amo tes…
riscv-non-isa · Oct 16, 2023 · 544665f · 544665f
2 parents 751348f + c2022af
commit 544665f
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [3.7.5] - 2023-10-11
+Add missing check ISA fields in recently modified div and amo tests
+
 ## [3.7.4] - 2023-10-04
 - Fix typos in CONTRIBUTION.md
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S b/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S b/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S b/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S b/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S b/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/M/src/div-01.S b/riscv-test-suite/rv32i_m/M/src/div-01.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoadd.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoadd.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoadd.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoadd.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoadd.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoand.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoand.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoand.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoand.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoand.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amomax.d-01.S b/riscv-test-suite/rv64i_m/A/src/amomax.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amomax.w-01.S b/riscv-test-suite/rv64i_m/A/src/amomax.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomax.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amomaxu.d-01.S b/riscv-test-suite/rv64i_m/A/src/amomaxu.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amomaxu.w-01.S b/riscv-test-suite/rv64i_m/A/src/amomaxu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomaxu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amomin.d-01.S b/riscv-test-suite/rv64i_m/A/src/amomin.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amomin.w-01.S b/riscv-test-suite/rv64i_m/A/src/amomin.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amomin.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amominu.d-01.S b/riscv-test-suite/rv64i_m/A/src/amominu.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amominu.w-01.S b/riscv-test-suite/rv64i_m/A/src/amominu.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amominu.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoor.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoor.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoor.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoswap.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoswap.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoswap.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoswap.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoswap.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoxor.d-01.S b/riscv-test-suite/rv64i_m/A/src/amoxor.d-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.d)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S b/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*);def TEST_CASE_1=True;",amoxor.w)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/M/src/div-01.S b/riscv-test-suite/rv64i_m/M/src/div-01.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",div)
 
 RVTEST_SIGBASE(x1,signature_x1_1)