Merge branch 'riscv-non-isa:main' into master

CHANGELOG.md

@@ -1,4 +1,11 @@
 # CHANGELOG
+## [3.8.3] - 2023-11-30
+- Add Zicond ISA extension support
+
+## [3.8.4] - 2023-11-30
+
+- Added test suites for `zcb` from code size reduction extension.
+- Added test macro for instructions with single operand.
 
 ## [3.8.3] -- 2013-12-15
 - Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023

coverage/zicond.cgf

@@ -0,0 +1,37 @@
+czero.eqz:
+    config: 
+      - check ISA:=regex(.*Zicond.*)
+    opcode: 
+      czero.eqz: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+czero.nez:
+    config: 
+      - check ISA:=regex(.*Zicond.*)
+    opcode: 
+      czero.nez: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]

riscv-test-suite/env/test_macros.h

@@ -919,7 +919,14 @@ ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
       inst destreg, x2,imm		;\
       )
 
-//Tests for instructions with a single register operand
+//Tests for instructions with single (rd/rs1) register operand.
+#define TEST_CRD_OP(inst, destreg, correctval, val1, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(destreg, MASK_XLEN(val1))		;\
+      inst destreg		;\
+      )
+
+//Tests for instructions with a destination and single source register operand
 #define TEST_RD_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) \
   TEST_CMV_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg)
 

riscv-test-suite/rv32i_m/C/src/clbu-01.S

@@ -0,0 +1,132 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.11.1
+// timestamp : Tue Jun 20 09:43:04 2023 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /home/abd/abd-data/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/abd/abd-data/riscv-ctg/sample_cgfs/rv32i_zcb.cgf \
+ \
+//                  -- xlen 32  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.lbu instruction of the RISC-V RV32_Zca_Zcb extension for the clbu covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I_Zca_Zcb")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu)
+
+RVTEST_SIGBASE(x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rd==x10, rs1==x14, imm_val == 0, 
+// opcode: c.lbu; op1:x14; dest:x10; immval:0x0
+TEST_LOAD(x1,x2,0,x14,x10,0x0,0*XLEN/8,c.lbu,0)
+
+inst_1:
+// rs1 == rd, rd==x13, rs1==x13, imm_val == 1, 
+// opcode: c.lbu; op1:x13; dest:x13; immval:0x1
+TEST_LOAD(x1,x2,0,x13,x13,0x1,1*XLEN/8,c.lbu,0)
+
+inst_2:
+// rd==x11, rs1==x10, imm_val == 2, 
+// opcode: c.lbu; op1:x10; dest:x11; immval:0x2
+TEST_LOAD(x1,x2,0,x10,x11,0x2,2*XLEN/8,c.lbu,0)
+
+inst_3:
+// rd==x12, rs1==x15, imm_val == 3, 
+// opcode: c.lbu; op1:x15; dest:x12; immval:0x3
+TEST_LOAD(x1,x2,0,x15,x12,0x3,3*XLEN/8,c.lbu,0)
+
+inst_4:
+// rd==x15, rs1==x11, 
+// opcode: c.lbu; op1:x11; dest:x15; immval:0x0
+TEST_LOAD(x1,x2,0,x11,x15,0x0,4*XLEN/8,c.lbu,0)
+
+inst_5:
+// rd==x9, rs1==x12, 
+// opcode: c.lbu; op1:x12; dest:x9; immval:0x0
+TEST_LOAD(x1,x2,0,x12,x9,0x0,5*XLEN/8,c.lbu,0)
+
+inst_6:
+// rd==x14, rs1==x9, 
+// opcode: c.lbu; op1:x9; dest:x14; immval:0x0
+TEST_LOAD(x1,x2,0,x9,x14,0x0,6*XLEN/8,c.lbu,0)
+
+inst_7:
+// rd==x8, 
+// opcode: c.lbu; op1:x12; dest:x8; immval:0x0
+TEST_LOAD(x1,x2,0,x12,x8,0x0,7*XLEN/8,c.lbu,0)
+
+inst_8:
+// rs1==x8, 
+// opcode: c.lbu; op1:x8; dest:x14; immval:0x0
+TEST_LOAD(x1,x2,0,x8,x14,0x0,8*XLEN/8,c.lbu,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+
+
+signature_x1_0:
+    .fill 0*((XLEN/8)/4),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 9*((XLEN/8)/4),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+tsig_begin_canary:
+CANARY;
+
+mtrap_sigptr:
+    .fill 64*XLEN/32,4,0xdeadbeef
+
+tsig_end_canary:
+CANARY;
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*XLEN/32,4,0xdeadbeef
+
+#endif
+
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END

riscv-test-suite/rv32i_m/C/src/clh-01.S

@@ -0,0 +1,127 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.11.1
+// timestamp : Tue Jun 20 09:43:04 2023 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /home/abd/abd-data/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/abd/abd-data/riscv-ctg/sample_cgfs/rv32i_zcb.cgf \
+ \
+//                  -- xlen 32  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.lh instruction of the RISC-V RV32_Zca_Zcb extension for the clh covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I_Zca_Zcb")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh)
+
+RVTEST_SIGBASE(x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rd==x14, rs1==x11, imm_val == 0, 
+// opcode: c.lh; op1:x11; dest:x14; immval:0x0
+TEST_LOAD(x1,x2,0,x11,x14,0x0,0*XLEN/8,c.lh,0)
+
+inst_1:
+// rs1 == rd, rd==x13, rs1==x13, imm_val == 2, 
+// opcode: c.lh; op1:x13; dest:x13; immval:0x2
+TEST_LOAD(x1,x2,0,x13,x13,0x2,1*XLEN/8,c.lh,0)
+
+inst_2:
+// rd==x12, rs1==x9, 
+// opcode: c.lh; op1:x9; dest:x12; immval:0x0
+TEST_LOAD(x1,x2,0,x9,x12,0x0,2*XLEN/8,c.lh,0)
+
+inst_3:
+// rd==x15, rs1==x8, 
+// opcode: c.lh; op1:x8; dest:x15; immval:0x0
+TEST_LOAD(x1,x2,0,x8,x15,0x0,3*XLEN/8,c.lh,0)
+
+inst_4:
+// rd==x11, rs1==x10, 
+// opcode: c.lh; op1:x10; dest:x11; immval:0x0
+TEST_LOAD(x1,x2,0,x10,x11,0x0,4*XLEN/8,c.lh,0)
+
+inst_5:
+// rd==x8, rs1==x14, 
+// opcode: c.lh; op1:x14; dest:x8; immval:0x0
+TEST_LOAD(x1,x2,0,x14,x8,0x0,5*XLEN/8,c.lh,0)
+
+inst_6:
+// rd==x9, rs1==x12, 
+// opcode: c.lh; op1:x12; dest:x9; immval:0x0
+TEST_LOAD(x1,x2,0,x12,x9,0x0,6*XLEN/8,c.lh,0)
+
+inst_7:
+// rd==x10, rs1==x15, 
+// opcode: c.lh; op1:x15; dest:x10; immval:0x0
+TEST_LOAD(x1,x2,0,x15,x10,0x0,7*XLEN/8,c.lh,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+
+
+signature_x1_0:
+    .fill 0*((XLEN/8)/4),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*((XLEN/8)/4),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+tsig_begin_canary:
+CANARY;
+
+mtrap_sigptr:
+    .fill 64*XLEN/32,4,0xdeadbeef
+
+tsig_end_canary:
+CANARY;
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*XLEN/32,4,0xdeadbeef
+
+#endif
+
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END