Merge branch 'dev' into pmm_acts

riscv-non-isa · Oct 24, 2024 · 2b1624e · 2b1624e
2 parents 40ae6fc + 2980588
commit 2b1624e
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diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
@@ -27,6 +27,8 @@ jobs:
   ACT-sail-spike:
     name: ACT-sail-spike (RV${{ matrix.xlen }})
     runs-on: ubuntu-22.04
+    # Set a 60-minute time limit for this job
+    timeout-minutes: 60
     strategy:
       fail-fast: false
       matrix:
@@ -42,7 +44,8 @@ jobs:
           sudo apt-get update
           sudo apt-get install -y python3 python3-pip python3-venv
           sudo apt-get install -y gcc git autoconf automake libtool curl make unzip
-          sudo apt-get install autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev libslirp-dev pkg-config
+          sudo apt-get install -y autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev libslirp-dev pkg-config
+          sudo apt-get install -y device-tree-compiler libboost-regex-dev libboost-system-dev
           pip3 install git+https://github.com/riscv/riscof.git
       
       - name: Build RISCV-GNU Toolchain (${{ matrix.xlen }} bit)
@@ -61,29 +64,113 @@ jobs:
         run: |
           cd riscv-ctg
           pip3 install --editable .
-      
+
+      - name: Get Latest Spike Commit
+        run: |
+              SPIKE_HASH=$(git ls-remote https://github.com/riscv/riscv-isa-sim.git HEAD | awk '{ print $1}')
+              echo "SPIKE_HASH=$SPIKE_HASH" >> "$GITHUB_ENV"
+
+      - name: Restore cached Spike
+        id: cache-spike-restore
+        uses: actions/cache/restore@v4
+        with:
+          path: ${{ github.workspace }}/spike
+          key: spike-${{ env.SPIKE_HASH }}-RV${{ matrix.xlen }}
+
       - name: Install Spike
+        if: steps.cache-spike-restore.outputs.cache-hit != 'true'
         run: |
           git clone https://github.com/riscv/riscv-isa-sim.git
-          sudo apt-get install device-tree-compiler libboost-regex-dev libboost-system-dev
           cd riscv-isa-sim
           mkdir build
           cd build
-          ../configure --prefix=$GITHUB_WORKSPACE/riscv64
+          ../configure --prefix=$GITHUB_WORKSPACE/spike
           make -j$(nproc)
-          sudo make install
-          echo $GITHUB_WORKSPACE/riscv64/bin >> $GITHUB_PATH      
+          make install
+
+      - name: Save cached Spike
+        if: steps.cache-spike-restore.outputs.cache-hit != 'true'
+        id: cache-spike-save
+        uses: actions/cache/save@v4
+        with:
+          path: ${{ github.workspace }}/spike
+          key: ${{ steps.cache-spike-restore.outputs.cache-primary-key }}
+
+      - name: Get Latest Sail Commit
+        run: |
+              SAIL_HASH=$(git ls-remote https://github.com/riscv/sail-riscv.git HEAD | awk '{ print $1}')
+              echo "SAIL_HASH=$SAIL_HASH" >> "$GITHUB_ENV"
+
+      - name: Restore cached Sail
+        id: cache-sail-restore
+        uses: actions/cache/restore@v4
+        with:
+          path: ${{ github.workspace }}/sail
+          key: sail-${{ env.SAIL_HASH }}-RV${{ matrix.xlen }}
 
       - name: Install Sail
+        if: steps.cache-sail-restore.outputs.cache-hit != 'true'
         run: |
           sudo mkdir -p /usr/local
           curl --location https://github.com/rems-project/sail/releases/download/0.18-linux-binary/sail.tar.gz | sudo tar xvz --directory=/usr/local --strip-components=1
           git clone https://github.com/riscv/sail-riscv.git
           cd sail-riscv
           ARCH=RV${{ matrix.xlen }} make
-          echo $PWD/c_emulator >> $GITHUB_PATH            
+          mkdir -p $GITHUB_WORKSPACE/sail
+          mv c_emulator/riscv_sim_RV${{ matrix.xlen }} $GITHUB_WORKSPACE/sail/riscv_sim_RV${{ matrix.xlen }}
+
+      - name: Save cached Sail
+        if: steps.cache-sail-restore.outputs.cache-hit != 'true'
+        id: cache-sail-save
+        uses: actions/cache/save@v4
+        with:
+          path: ${{ github.workspace }}/sail
+          key: ${{ steps.cache-sail-restore.outputs.cache-primary-key }}
+
+      - name: Set PATH
+        run: |
+              echo $GITHUB_WORKSPACE/spike/bin >> $GITHUB_PATH
+              echo $GITHUB_WORKSPACE/sail >> $GITHUB_PATH
       
       - name: Config and run riscof for RV${{ matrix.xlen }}
         run: |
           cd riscof-plugins/rv${{ matrix.xlen }}
           riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m/ --env ../../riscv-test-suite/env
+
+      #Check the existance of the riscof work folder, and add the PATH to environment variable
+      - name: Check size and determine upload path
+        if: always()
+        id: check_size
+        run: |
+          work_folder="${{ github.workspace }}/riscof-plugins/rv${{ matrix.xlen }}/riscof_work/"
+          report_file="$work_folder/report.html"
+          if [ -d "$work_folder" ]; then
+            folder_size=$(du -sm "$work_folder" | cut -f1)
+            echo "Folder size: ${folder_size} MB"
+            if [ "$folder_size" -gt 1000 ]; then
+              echo "Size exceeds 1 GB. Checking if report exists."
+              if [ -f "$report_file" ]; then
+                echo "Uploading RISCOF generated report only."
+                echo "upload_path=$report_file" >> $GITHUB_ENV
+              else
+                echo "No report found. Skipping upload."
+                echo "upload_path=" >> $GITHUB_ENV
+              fi
+            else
+              echo "Size is within limit. Uploading complete RISCOF_WORK Folder."
+              echo "upload_path=$work_folder" >> $GITHUB_ENV
+            fi
+          else
+            echo "Folder does not exist. Skipping upload."
+            echo "upload_path=" >> $GITHUB_ENV
+          fi
+
+      # Upload the appropriate artifact (folder or report) and skip in case not exists
+      - name: Upload riscof artifact for rv${{ matrix.xlen }}
+        if: always() && env.upload_path != ''
+        uses: actions/upload-artifact@v4
+        with:
+          name: riscof-artifact-rv${{ matrix.xlen }}
+          path: ${{ env.upload_path }}
+          compression-level: 6
+          overwrite: true
diff --git a/README.md b/README.md
@@ -73,8 +73,8 @@ The files [`COPYING.BSD`](./COPYING.BSD), [`COPYING.APACHE`](./COPYING.APACHE) a
 ## Quick Links:
 
 - RISCOF \[[DOCS](https://riscof.readthedocs.io/en/latest/)\] \[[REPO](https://github.com/riscv-software-src/riscof)\]: This is the next version of the architectural test framework currently under development
-- RISCV-ISAC \[[DOCS](https://riscv-isac.readthedocs.io/en/latest/index.html)\] \[[REPO](https://github.com/riscv-software-src/riscv-isac)\] : This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests.
-- RISCV-CTG: \[[DOCS](https://riscv-ctg.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv-software-src/riscv-ctg)\]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository.
+- RISCV-ISAC \[[DOCS](https://riscv-isac.readthedocs.io/en/latest/index.html)\]: This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests.
+- RISCV-CTG: \[[DOCS](https://riscv-ctg.readthedocs.io/en/latest/index.html)\]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository.
 - [Videos](https://youtu.be/VIW1or1Oubo): This Global Forum 2020 video provides an introduction to the above mentioned tools
 - [riscvOVPsim](https://github.com/riscv-ovpsim/imperas-riscv-tests): Imperas freeware RISC-V reference simulator for compliance testing
 - [riscvOVPsimPlus](https://www.ovpworld.org/riscvOVPsimPlus/): Imperas enhanced freeware RISC-V reference simulator for test development and verification
@@ -209,22 +209,23 @@ Note: Use sudo if the installation path requires administrative privileges.
 
 
 ### 2. SAIL (SAIL C-emulator)
+First install the [Sail Compiler](https://github.com/rems-project/sail/). It is recommended to use the pre-compiled [binary release](https://github.com/rems-project/sail/releases). This can be performed as follows:
 
 ```bash
-$ sudo apt-get install opam build-essential libgmp-dev z3 pkg-config zlib1g-dev
-$ opam init -y --disable-sandboxing
-$ opam switch create ocaml-base-compiler
-$ opam install sail -y
-$ eval $(opam config env)
+$ sudo apt-get install libgmp-dev pkg-config zlib1g-dev curl
+$ curl --location https://github.com/rems-project/sail/releases/download/0.18-linux-binary/sail.tar.gz | [sudo] tar xvz --directory=/path/to/install --strip-components=1
+```
+Note: Make sure to add the path `/path/to/install` to your `$PATH`.
+
+Then build the RISC-V Sail Model:
+```bash
 $ git clone https://github.com/riscv/sail-riscv.git
 $ cd sail-riscv
 $ ARCH=RV32 make
 $ ARCH=RV64 make
-$ ln -s sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
-$ ln -s sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 ```
 
-This will create a C simulator in `c_emulator/riscv_sim_RV64` and `c_emulator/riscv_sim_RV32`. You will need to add these paths to your `$PATH` or create an alias to execute them from the command line.
+This will create a C simulator in `c_emulator/riscv_sim_RV64` and `c_emulator/riscv_sim_RV32`. You will need to add this path to your `$PATH` or create an alias to execute them from the command line.
 
 
 ## Necessary Env Files

diff --git a/riscv-ctg/riscv_ctg/ctg.py b/riscv-ctg/riscv_ctg/ctg.py
@@ -106,7 +106,7 @@ def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, ma
     logger.info('Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.')
     logger.info('All Rights Reserved.')
     logger.info("Copying env folder to Output directory.")
-    env_dir = os.path.join(out,"env")
+    env_dir = os.path.expanduser("~/riscv-arch-test/riscv-test-suite/env")
     if not os.path.exists(env_dir):
         shutil.copytree(const.env,env_dir)
     xlen = int(xlen_arg)

diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py
@@ -888,7 +888,7 @@ def eval_inst_coverage(coverpoints,instr):
             if (is_fp_instruction(insn)):
                 insn = "fadd.s"
             instr_obj = instructionObject(None, insn, None)
-            ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))})
+            ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen, 'inxFlag': self.inxFlag, 'xlen': self.xlen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))})
 
             if ext_specific_vars is not None:
                 var_dict.update(ext_specific_vars)

diff --git a/riscv-ctg/riscv_ctg/requirements.txt b/riscv-ctg/riscv_ctg/requirements.txt
diff --git a/riscv-ctg/riscv_ctg/requirements.txt b/riscv-ctg/riscv_ctg/requirements.txt
@@ -0,0 +1 @@
+../../requirements.txt
diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py
@@ -25,7 +25,7 @@
         'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
         'bset','zext.h','sext.h','sext.b','zext.b','zext.w','minu','maxu','orc.b','add.uw','sh1add.uw',\
         'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
-        'bclri','bexti','binvi','bseti','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu','c.flwsp',\
+        'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip','gorci','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu','c.flwsp',\
         'c.not', 'c.sext.b','c.sext.h','c.zext.b','c.zext.h','c.zext.w','sc.w','lr.w','sc.d','lr.d']
 unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
         'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\

diff --git a/riscv-isac/riscv_isac/cgf_normalize.py b/riscv-isac/riscv_isac/cgf_normalize.py
@@ -580,10 +580,10 @@ def expand_cgf(cgf_files, xlen,flen, log_redundant=False):
                     if len(cgf[labels]['mnemonics'].keys()) > 1:
                         logger.error(f'Multiple instruction mnemonics found when base_op label defined in {labels} label.')
 
-            # Substitute instruction aliases with equivalent tuple of instructions   
+            # Substitute instruction aliases with equivalent tuple of instructions
             if 'cross_comb' in cats:
                 temp = cats['cross_comb']
-                
+
                 for covp, covge in dict(temp).items():
                     data = covp.split('::')
                     ops = data[0].replace(' ', '')[1:-1].split(':')
@@ -592,14 +592,14 @@ def expand_cgf(cgf_files, xlen,flen, log_redundant=False):
                         exp_alias = utils.import_instr_alias(ops[i])
                         if exp_alias != None:
                             ops[i] = tuple(exp_alias).__str__().replace("'", '').replace(" ", '')
-                    
+
                     data[0] = '[' + ':'.join(ops) + ']'
                     data = '::'.join(data)
                     del temp[covp]
                     temp[data] = covge
-                
-                cgf[labels].insert(1, 'cross_comb', temp)                 
-            
+
+                cgf[labels].insert(1, 'cross_comb', temp)
+
             l = len(cats.items())
             i = 0
             for label,node in cats.items():
@@ -618,7 +618,13 @@ def expand_cgf(cgf_files, xlen,flen, log_redundant=False):
                                 for cp,comment in exp_cp:
                                     if log_redundant and cp in cgf[labels][label]:
                                         logger.warn(f'Redundant coverpoint during normalization: {cp}')
-                                    cgf[labels][label].insert(l+i,cp,coverage,comment=comment)
+
+                                    # PyYAML has catastrophic performance adding comments
+                                    # so only do it for the first 100 entries.
+                                    if i < 100:
+                                        cgf[labels][label].yaml_add_eol_comment(comment, key=cp)
+                                    else:
+                                        cgf[labels][label][cp] = coverage
+
                                     i += 1
     return dict(cgf)
-
diff --git a/riscv-isac/riscv_isac/data/rvopcodesdecoder.py b/riscv-isac/riscv_isac/data/rvopcodesdecoder.py
@@ -400,7 +400,7 @@ def decode(self, instrObj_temp):
                     if any([instr_name.startswith(x) for x in [
                             'fsh', 'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l','fcvt.h','fmv.h','flh','fclass','fsqrt','fmax','fmin','fadd','fsub','feq','fle','flt','fmul','fdiv','fsgnj','fsgnjn','fsgnjx']]):
                         treg = 'x'
-                    temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg
+                    temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg)
                     if 'p' in arg:
                         temp_instrobj.rd = (8+int(get_arg_val(arg)(mcode), 2), treg)
                     else:
@@ -452,6 +452,10 @@ def decode(self, instrObj_temp):
                     temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2)
                 if arg == 'csr':
                     temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'bs':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'rnum':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
                 if arg.find('imm') != -1:
                     if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']:
                         imm = get_arg_val(arg)(mcode)

diff --git a/riscv-isac/riscv_isac/plugins/internaldecoder.py b/riscv-isac/riscv_isac/plugins/internaldecoder.py
@@ -598,10 +598,10 @@ def arithi_ops(self, instrObj):
 
         if funct3 == 0b001:
             if funct7 == 0b0000100:
-                if instrObj.arch == 'rv32':
-                    instrObj.instr_name = 'zip'
-                    instrObj.rs1= rs1
-                    instrObj.rd = rd
+                if self.arch == 'rv32':
+                   instrObj.instr_name = 'zip'
+                   instrObj.rs1= rs1
+                   instrObj.rd = rd
             elif sbi == 0b0100100 or  sbi == 0b010010:
                 instrObj.rs1 = rs1
                 instrObj.rd = rd
@@ -720,7 +720,7 @@ def arithi_ops(self, instrObj):
 
         if funct3 == 0b101:
             if funct7 == 0b0000100:
-                if instrObj.arch == 'rv32':
+                if self.arch == 'rv32':
                     instrObj.instr_name = 'unzip'
                     instrObj.rs1= rs1
                     instrObj.rd = rd
@@ -1210,15 +1210,10 @@ def arith_ops(self, instrObj):
                 instrObj.rs2 = rs2
                 instrObj.rd = rd
             elif funct7 == 0b0000100:
-                if rs2[0] == 0b0:
-                    instrObj.instr_name = 'zext.h'
-                    instrObj.rs1 = rs1
-                    instrObj.rd = rd
-                else:
-                    instrObj.instr_name = 'pack'
-                    instrObj.rs1 = rs1
-                    instrObj.rs2 = rs2
-                    instrObj.rd = rd
+                instrObj.instr_name = 'pack'
+                instrObj.rs1 = rs1
+                instrObj.rs2 = rs2
+                instrObj.rd = rd
             elif funct7 == 0b0000101:
                 instrObj.instr_name = 'min'
                 instrObj.rs1 = rs1
@@ -1499,15 +1494,14 @@ def rv64i_arith_ops(self, instrObj):
 
         if funct3 == 0b100:
             if funct7 == 0b0000100:
-                if rs2[0] == 0b0:
-                    instrObj.instr_name = 'zext.h'
-                    instrObj.rs1 = rs1
-                    instrObj.rd = rd
-                else:
-                    instrObj.instr_name = 'packw'
-                    instrObj.rs1 = rs1
-                    instrObj.rs2 = rs2
-                    instrObj.rd = rd
+# packw and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
+# for zext.h rs2 is always 0, if packw instruction is used with x0 as rs2
+# then cannot distinguish from each other, hence using isa to differentiate.
+# zext.h is part of Zbb, packw is part of Zbkb
+                instrObj.instr_name = 'packw'
+                instrObj.rs1 = rs1
+                instrObj.rs2 = rs2
+                instrObj.rd = rd
             elif funct7 == 0b0010000:
                 instrObj.instr_name = 'sh2add.uw'
                 instrObj.rs1 = rs1