From upstream

contrib/loaders/flash/rsl10/rom_launcher.S

@@ -21,7 +21,7 @@
 	.global _start
 _start:
 launch_program_in_rom:
-    // variables are already set, addres to jump is in r3
+    // variables are already set, address to jump is in r3
     blx r3
 exit:
 	// Wait for OpenOCD

doc/openocd.texi

@@ -8519,13 +8519,90 @@ openocd -f board/digilent_zedboard.cfg -c "init" \
 @end example
 
 
-
 @deffn {Command} {virtex2 read_stat} num
 Reads and displays the Virtex-II status register (STAT)
 for FPGA @var{num}.
 @end deffn
 @end deffn
 
+
+
+@deffn {FPGA Driver} {lattice} [family]
+The FGPA families ECP2, ECP3, ECP5, Certus and CertusPro by Lattice are supported.
+This driver can be used to load the bitstream into the FPGA or read the status register and read/write the usercode register.
+
+The option @option{family} is one of @var{ecp2 ecp3 ecp5 certus}. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
+
+@deffn {Command} {lattice read_status} num
+Reads and displays the status register
+for FPGA @var{num}.
+@end deffn
+
+@deffn {Command} {lattice read_user} num
+Reads and displays the user register
+for FPGA @var{num}.
+@end deffn
+
+@deffn {Command} {lattice write_user} num val
+Writes the user register.
+for FPGA @var{num} with value @var{val}.
+@end deffn
+
+@deffn {Command} {lattice set_preload} num length
+Set the length of the register for the preload. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
+The load command for the FPGA @var{num} will use a length for the preload of @var{length}.
+@end deffn
+@end deffn
+
+
+@deffn {FPGA Driver} {efinix}
+Both families (Trion and Titanium) sold by Efinix are supported as both use the same protocol for In-System Configuration.
+This driver can be used to load the bitstream into the FPGA.
+@end deffn
+
+
+@deffn {FPGA Driver} {intel} [@option{family}]
+This driver can be used to load the bitstream into Intel (former Altera) FPGAs.
+The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10, Arria II are supported.
+@c Arria V and Arria 10, MAX II, MAX V, MAX10)
+
+The option @option{family} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}.
+This is needed when the JTAG ID of the device is ambiguous (same ID is used for chips in different families).
+
+As input file format the driver supports a '.rbf' (raw bitstream file) file. The '.rbf' file can be generated
+from a '.sof' file with @verb{|quartus_cpf -c blinker.sof blinker.rbf|}
+
+Defines a new PLD device, an FPGA of the Cyclone III family, using the TAP named @verb{|cycloneiii.tap|}:
+@example
+pld device intel cycloneiii.tap cycloneiii
+@end example
+
+@deffn {Command} {intel set_bscan} num len
+Set boundary scan register length of FPGA @var{num} to @var{len}. This is needed because the
+length can vary between chips with the same JTAG ID.
+@end deffn
+
+@deffn {Command} {intel set_check_pos} num pos
+Selects the position @var{pos} in the boundary-scan register. The bit at this
+position is checked after loading the bitstream and must be '1', which is the case when no error occurred.
+With a value of -1 for @var{pos} the check will be omitted.
+@end deffn
+@end deffn
+
+
+@deffn {FPGA Driver} {gowin}
+This driver can be used to load the bitstream into FPGAs from Gowin.
+It is possible to program the SRAM. Programming the flash is not supported.
+The files @verb{|.fs|} and @verb{|.bin|} generated by Gowin FPGA Designer are supported.
+@end deffn
+
+
+@deffn {FPGA Driver} {gatemate}
+This driver can be used to load the bitstream into GateMate FPGAs form CologneChip.
+The files @verb{|.bit|} and @verb{|.cfg|} both generated by p_r tool from CologneChip are supported.
+@end deffn
+
+
 @node General Commands
 @chapter General Commands
 @cindex commands
@@ -11370,6 +11447,46 @@ Stop current trace as started by the tracestart command.
 Dump trace memory to a file.
 @end deffn
 
+@section Espressif Specific Commands
+
+@deffn {Command} {esp apptrace} (start <destination> [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]])
+Starts
+@uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}.
+Data will be stored to specified destination. Available destinations are:
+@itemize @bullet
+@item @code{file://<outfile>} - Save trace logs into file.
+@item @code{tcp://<host>:<port>} - Send trace logs to tcp port on specified host. OpenOCD will act as a tcp client.
+@item @code{con:} - Print trace logs to the stdout.
+@end itemize
+Other parameters will be same for each destination.
+@itemize @bullet
+@item @code{poll_period} - trace data polling period in ms.
+@item @code{trace_size} - maximum trace data size.
+Tracing will be stopped automatically when that amount is reached.
+Use "-1" to disable the limitation.
+@item @code{stop_tmo} - Data reception timeout in ms.
+Tracing will be stopped automatically when no data is received within that period.
+@item @code{wait4halt} - if non-zero then wait for target to be halted before tracing start.
+@item @code{skip_size} - amount of tracing data to be skipped before writing it to destination.
+@end itemize
+@end deffn
+
+@deffn {Command} {esp apptrace} (stop)
+Stops tracing started with above command.
+@end deffn
+
+@deffn {Command} {esp apptrace} (status)
+Requests ongoing tracing status.
+@end deffn
+
+@deffn {Command} {esp apptrace} (dump file://<outfile>)
+Dumps tracing data from target buffer. It can be useful to dump the latest data
+buffered on target for post-mortem analysis. For example when target starts tracing automatically
+w/o OpenOCD command and keeps only the latest data window which fit into the buffer.
+@uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}.
+Data will be stored to specified destination.
+@end deffn
+
 @anchor{softwaredebugmessagesandtracing}
 @section Software Debug Messages and Tracing
 @cindex Linux-ARM DCC support

src/flash/nand/driver.c

@@ -13,25 +13,6 @@
 #include "core.h"
 #include "driver.h"
 
-/* NAND flash controller
- */
-extern struct nand_flash_controller nonce_nand_controller;
-extern struct nand_flash_controller davinci_nand_controller;
-extern struct nand_flash_controller lpc3180_nand_controller;
-extern struct nand_flash_controller lpc32xx_nand_controller;
-extern struct nand_flash_controller orion_nand_controller;
-extern struct nand_flash_controller s3c2410_nand_controller;
-extern struct nand_flash_controller s3c2412_nand_controller;
-extern struct nand_flash_controller s3c2440_nand_controller;
-extern struct nand_flash_controller s3c2443_nand_controller;
-extern struct nand_flash_controller s3c6400_nand_controller;
-extern struct nand_flash_controller mxc_nand_flash_controller;
-extern struct nand_flash_controller imx31_nand_flash_controller;
-extern struct nand_flash_controller at91sam9_nand_controller;
-extern struct nand_flash_controller nuc910_nand_controller;
-
-/* extern struct nand_flash_controller boundary_scan_nand_controller; */
-
 static struct nand_flash_controller *nand_flash_controllers[] = {
 	&nonce_nand_controller,
 	&davinci_nand_controller,
@@ -47,7 +28,6 @@ static struct nand_flash_controller *nand_flash_controllers[] = {
 	&imx31_nand_flash_controller,
 	&at91sam9_nand_controller,
 	&nuc910_nand_controller,
-/*	&boundary_scan_nand_controller, */
 	NULL
 };
 

src/flash/nand/driver.h

@@ -89,4 +89,19 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *);
  */
 int nand_driver_walk(nand_driver_walker_t f, void *x);
 
+extern struct nand_flash_controller at91sam9_nand_controller;
+extern struct nand_flash_controller davinci_nand_controller;
+extern struct nand_flash_controller imx31_nand_flash_controller;
+extern struct nand_flash_controller lpc3180_nand_controller;
+extern struct nand_flash_controller lpc32xx_nand_controller;
+extern struct nand_flash_controller mxc_nand_flash_controller;
+extern struct nand_flash_controller nonce_nand_controller;
+extern struct nand_flash_controller nuc910_nand_controller;
+extern struct nand_flash_controller orion_nand_controller;
+extern struct nand_flash_controller s3c2410_nand_controller;
+extern struct nand_flash_controller s3c2412_nand_controller;
+extern struct nand_flash_controller s3c2440_nand_controller;
+extern struct nand_flash_controller s3c2443_nand_controller;
+extern struct nand_flash_controller s3c6400_nand_controller;
+
 #endif /* OPENOCD_FLASH_NAND_DRIVER_H */

src/flash/nand/lpc32xx.c

@@ -1029,7 +1029,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 
 	LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
 		"data_size=%" PRIu32 ", oob_size=%" PRIu32,
-		page, data != 0, oob != 0, data_size, oob_size);
+		page, !!data, !!oob, data_size, oob_size);
 
 	target_mem_base = pworking_area->address;
 	/*

src/flash/nor/at91sam3.c

@@ -67,8 +67,6 @@
 #define  OFFSET_EFC_FSR   8
 #define  OFFSET_EFC_FRR   12
 
-extern const struct flash_driver at91sam3_flash;
-
 static float _tomhz(uint32_t freq_hz)
 {
 	float f;

src/flash/nor/at91sam4.c

@@ -62,8 +62,6 @@
 #define  OFFSET_EFC_FSR   8
 #define  OFFSET_EFC_FRR   12
 
-extern const struct flash_driver at91sam4_flash;
-
 static float _tomhz(uint32_t freq_hz)
 {
 	float f;

src/flash/nor/at91samd.c

@@ -78,7 +78,7 @@
 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
 
 /* Bits to mask out lockbits in user row */
-#define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)
+#define NVMUSERROW_LOCKBIT_MASK 0x0000FFFFFFFFFFFFULL
 
 struct samd_part {
 	uint8_t id;
@@ -316,31 +316,31 @@ struct samd_family {
 static const struct samd_family samd_families[] = {
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
 		samd20_parts, ARRAY_SIZE(samd20_parts),
-		(uint64_t)0xFFFF01FFFE01FF77 },
+		0xFFFF01FFFE01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
 		samd21_parts, ARRAY_SIZE(samd21_parts),
-		(uint64_t)0xFFFF01FFFE01FF77 },
+		0xFFFF01FFFE01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
 		samd09_parts, ARRAY_SIZE(samd09_parts),
-		(uint64_t)0xFFFF01FFFE01FF77 },
+		0xFFFF01FFFE01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
 		samd10_parts, ARRAY_SIZE(samd10_parts),
-		(uint64_t)0xFFFF01FFFE01FF77 },
+		0xFFFF01FFFE01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
 		samd11_parts, ARRAY_SIZE(samd11_parts),
-		(uint64_t)0xFFFF01FFFE01FF77 },
+		0xFFFF01FFFE01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
 		saml21_parts, ARRAY_SIZE(saml21_parts),
-		(uint64_t)0xFFFF03FFFC01FF77 },
+		0xFFFF03FFFC01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
 		saml22_parts, ARRAY_SIZE(saml22_parts),
-		(uint64_t)0xFFFF03FFFC01FF77 },
+		0xFFFF03FFFC01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
 		samc20_parts, ARRAY_SIZE(samc20_parts),
-		(uint64_t)0xFFFF03FFFC01FF77 },
+		0xFFFF03FFFC01FF77ULL },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
 		samc21_parts, ARRAY_SIZE(samc21_parts),
-		(uint64_t)0xFFFF03FFFC01FF77 },
+		0xFFFF03FFFC01FF77ULL },
 };
 
 struct samd_info {

src/flash/nor/atsame5.c

@@ -93,7 +93,7 @@
 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
 
 /* Bits to mask user row */
-#define NVMUSERROW_SAM_E5_D5_MASK	((uint64_t)0x7FFF00FF3C007FFF)
+#define NVMUSERROW_SAM_E5_D5_MASK	0x7FFF00FF3C007FFFULL
 
 struct samd_part {
 	uint8_t id;

src/flash/nor/atsamv.c

@@ -53,8 +53,6 @@
 #define SAMV_PAGE_SIZE                 512
 #define SAMV_FLASH_BASE         0x00400000
 
-extern const struct flash_driver atsamv_flash;
-
 struct samv_flash_bank {
 	bool      probed;
 	unsigned size_bytes;

src/flash/nor/driver.h

@@ -237,4 +237,76 @@ struct flash_driver {
  */
 const struct flash_driver *flash_driver_find_by_name(const char *name);
 
+extern const struct flash_driver aduc702x_flash;
+extern const struct flash_driver aducm360_flash;
+extern const struct flash_driver ambiqmicro_flash;
+extern const struct flash_driver at91sam3_flash;
+extern const struct flash_driver at91sam4_flash;
+extern const struct flash_driver at91sam4l_flash;
+extern const struct flash_driver at91sam7_flash;
+extern const struct flash_driver at91samd_flash;
+extern const struct flash_driver ath79_flash;
+extern const struct flash_driver atsame5_flash;
+extern const struct flash_driver atsamv_flash;
+extern const struct flash_driver avr_flash;
+extern const struct flash_driver bluenrgx_flash;
+extern const struct flash_driver cc26xx_flash;
+extern const struct flash_driver cc3220sf_flash;
+extern const struct flash_driver cfi_flash;
+extern const struct flash_driver dsp5680xx_flash;
+extern const struct flash_driver efm32_flash;
+extern const struct flash_driver em357_flash;
+extern const struct flash_driver esirisc_flash;
+extern const struct flash_driver faux_flash;
+extern const struct flash_driver fespi_flash;
+extern const struct flash_driver gd32vf103_flash;
+extern const struct flash_driver fm3_flash;
+extern const struct flash_driver fm4_flash;
+extern const struct flash_driver jtagspi_flash;
+extern const struct flash_driver kinetis_flash;
+extern const struct flash_driver kinetis_ke_flash;
+extern const struct flash_driver lpc2000_flash;
+extern const struct flash_driver lpc288x_flash;
+extern const struct flash_driver lpc2900_flash;
+extern const struct flash_driver lpcspifi_flash;
+extern const struct flash_driver max32xxx_flash;
+extern const struct flash_driver mdr_flash;
+extern const struct flash_driver mrvlqspi_flash;
+extern const struct flash_driver msp432_flash;
+extern const struct flash_driver niietcm4_flash;
+extern const struct flash_driver npcx_flash;
+extern const struct flash_driver nrf51_flash;
+extern const struct flash_driver nrf5_flash;
+extern const struct flash_driver numicro_flash;
+extern const struct flash_driver ocl_flash;
+extern const struct flash_driver pic32mx_flash;
+extern const struct flash_driver psoc4_flash;
+extern const struct flash_driver psoc5lp_eeprom_flash;
+extern const struct flash_driver psoc5lp_flash;
+extern const struct flash_driver psoc5lp_nvl_flash;
+extern const struct flash_driver psoc6_flash;
+extern const struct flash_driver renesas_rpchf_flash;
+extern const struct flash_driver rp2040_flash;
+extern const struct flash_driver rsl10_flash;
+extern const struct flash_driver sh_qspi_flash;
+extern const struct flash_driver sim3x_flash;
+extern const struct flash_driver stellaris_flash;
+extern const struct flash_driver stm32f1x_flash;
+extern const struct flash_driver stm32f2x_flash;
+extern const struct flash_driver stm32h7x_flash;
+extern const struct flash_driver stm32l4x_flash;
+extern const struct flash_driver stm32lx_flash;
+extern const struct flash_driver stmqspi_flash;
+extern const struct flash_driver stmsmi_flash;
+extern const struct flash_driver str7x_flash;
+extern const struct flash_driver str9x_flash;
+extern const struct flash_driver str9xpec_flash;
+extern const struct flash_driver swm050_flash;
+extern const struct flash_driver tms470_flash;
+extern const struct flash_driver virtual_flash;
+extern const struct flash_driver w600_flash;
+extern const struct flash_driver xcf_flash;
+extern const struct flash_driver xmc1xxx_flash;
+extern const struct flash_driver xmc4xxx_flash;
+
 #endif /* OPENOCD_FLASH_NOR_DRIVER_H */