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Merge pull request #901 from aap-sc/aap-sc/refactor_reg_rw_progbuf
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[riscv] refactor functions that register read/write via progbuf
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@timsifive
timsifive authored Aug 17, 2023
2 parents 9260101 + a8fedeb commit f061623
Showing 1 changed file with 147 additions and 72 deletions.
219 changes: 147 additions & 72 deletions src/target/riscv/riscv-013.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1448,51 +1448,76 @@ static int internal_register_read64_progbuf_scratch(struct target *target,
return result;
}

/**
* This function reads a register by writing a program to program buffer and
* executing it.
*/
static int register_read_progbuf(struct target *target, uint64_t *value,
static int fpr_read_progbuf(struct target *target, uint64_t *value,
enum gdb_regno number)
{
assert(target->state == TARGET_HALTED);
assert(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31);

const unsigned int freg = number - GDB_REGNO_FPR0;

if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;

struct riscv_program program;
riscv_program_init(&program, target);
if (riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64) {
/* There are no instructions to move all the bits from a
* register, so we need to use some scratch RAM.
*/
if (riscv_program_insert(&program, fsd(freg, S0, 0)) != ERROR_OK)
return ERROR_FAIL;
return internal_register_read64_progbuf_scratch(target, &program, value);
}
if (riscv_program_insert(&program,
riscv_supports_extension(target, 'D') ?
fmv_x_d(S0, freg) : fmv_x_w(S0, freg)) != ERROR_OK)
return ERROR_FAIL;

if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
if (riscv_program_exec(&program, target) != ERROR_OK)
return ERROR_FAIL;

if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
const unsigned int freg = number - GDB_REGNO_FPR0;
return register_read_abstract(target, value, GDB_REGNO_S0) != ERROR_OK;
}

if (riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64) {
/* There are no instructions to move all the bits from a
* register, so we need to use some scratch RAM.
*/
if (riscv_program_insert(&program, fsd(freg, S0, 0)) != ERROR_OK)
return ERROR_FAIL;
return internal_register_read64_progbuf_scratch(target, &program,
value);
}
if (riscv_program_insert(&program,
riscv_supports_extension(target, 'D') ?
fmv_x_d(S0, freg) : fmv_x_w(S0, freg)) != ERROR_OK)
return ERROR_FAIL;
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
if (riscv_program_csrr(&program, S0, number) != ERROR_OK)
return ERROR_FAIL;
} else {
LOG_TARGET_ERROR(target, "Unsupported register: %s", gdb_regno_name(number));
static int csr_read_progbuf(struct target *target, uint64_t *value,
enum gdb_regno number)
{
assert(target->state == TARGET_HALTED);
assert(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095);

if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;
}

struct riscv_program program;
riscv_program_init(&program, target);
if (riscv_program_csrr(&program, S0, number) != ERROR_OK)
return ERROR_FAIL;
if (riscv_program_exec(&program, target) != ERROR_OK)
return ERROR_FAIL;

return register_read_abstract(target, value, GDB_REGNO_S0) != ERROR_OK;
}

/**
* This function reads a register by writing a program to program buffer and
* executing it.
*/
static int register_read_progbuf(struct target *target, uint64_t *value,
enum gdb_regno number)
{
assert(target->state == TARGET_HALTED);

if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
return fpr_read_progbuf(target, value, number);
else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
return csr_read_progbuf(target, value, number);

LOG_TARGET_ERROR(target, "Unexpected read of %s via program buffer.",
gdb_regno_name(number));
return ERROR_FAIL;
}

/**
* This function is used to write a 64-bit value to a register by executing a
* program.
Expand Down Expand Up @@ -1522,73 +1547,123 @@ static int internal_register_write64_progbuf_scratch(struct target *target,
return result;
}

/**
* This function writes a register by writing a program to program buffer and
* executing it.
*/
static int register_write_progbuf(struct target *target, enum gdb_regno number,
static int fpr_write_progbuf(struct target *target, enum gdb_regno number,
riscv_reg_t value)
{
assert(target->state == TARGET_HALTED);

struct riscv_program program;

riscv_program_init(&program, target);
assert(number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31);
const unsigned int freg = number - GDB_REGNO_FPR0;

if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;

if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64) {
struct riscv_program program;
riscv_program_init(&program, target);

if (riscv_supports_extension(target, 'D') && riscv_xlen(target) < 64) {
/* There are no instructions to move all the bits from a register,
* so we need to use some scratch RAM.
*/
const unsigned int freg = number - GDB_REGNO_FPR0;

if (riscv_program_insert(&program, fld(freg, S0, 0)) != ERROR_OK)
return ERROR_FAIL;
return internal_register_write64_progbuf_scratch(target, &program,
value);
return internal_register_write64_progbuf_scratch(target, &program, value);
}

if (register_write_abstract(target, GDB_REGNO_S0, value) != ERROR_OK)
return ERROR_FAIL;

if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
const unsigned int freg = number - GDB_REGNO_FPR0;
if (riscv_program_insert(&program,
riscv_supports_extension(target, 'D') ?
fmv_d_x(freg, S0) : fmv_w_x(freg, S0)) != ERROR_OK)
return ERROR_FAIL;

if (riscv_program_insert(&program,
riscv_supports_extension(target, 'D') ?
fmv_d_x(freg, S0) : fmv_w_x(freg, S0)) != ERROR_OK)
return ERROR_FAIL;
} else if (number == GDB_REGNO_VTYPE) {
if (riscv_save_register(target, GDB_REGNO_S1) != ERROR_OK)
return ERROR_FAIL;
if (riscv_program_insert(&program, csrr(S1, CSR_VL)) != ERROR_OK)
return ERROR_FAIL;
if (riscv_program_insert(&program, vsetvl(ZERO, S1, S0)) != ERROR_OK)
return ERROR_FAIL;
} else if (number == GDB_REGNO_VL) {
/* "The XLEN-bit-wide read-only vl CSR can only be updated by the
* vsetvli and vsetvl instructions, and the fault-only-rst vector
* load instruction variants."
*/
if (riscv_save_register(target, GDB_REGNO_S1) != ERROR_OK)
return ERROR_FAIL;
if (riscv_program_insert(&program, csrr(S1, CSR_VTYPE)) != ERROR_OK)
return ERROR_FAIL;
if (riscv_program_insert(&program, vsetvl(ZERO, S0, S1)) != ERROR_OK)
return ERROR_FAIL;
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
if (riscv_program_csrw(&program, S0, number) != ERROR_OK)
return ERROR_FAIL;
} else {
LOG_TARGET_ERROR(target, "Unsupported register (enum gdb_regno)(%d)", number);
return riscv_program_exec(&program, target);
}

static int vtype_write_progbuf(struct target *target, riscv_reg_t value)
{
assert(target->state == TARGET_HALTED);

if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;
}
if (register_write_abstract(target, GDB_REGNO_S0, value) != ERROR_OK)
return ERROR_FAIL;
if (riscv_save_register(target, GDB_REGNO_S1) != ERROR_OK)
return ERROR_FAIL;

struct riscv_program program;
riscv_program_init(&program, target);
if (riscv_program_insert(&program, csrr(S1, CSR_VL)) != ERROR_OK)
return ERROR_FAIL;
if (riscv_program_insert(&program, vsetvl(ZERO, S1, S0)) != ERROR_OK)
return ERROR_FAIL;

return riscv_program_exec(&program, target);
}

static int vl_write_progbuf(struct target *target, riscv_reg_t value)
{
assert(target->state == TARGET_HALTED);

if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;
if (register_write_abstract(target, GDB_REGNO_S0, value) != ERROR_OK)
return ERROR_FAIL;
if (riscv_save_register(target, GDB_REGNO_S1) != ERROR_OK)
return ERROR_FAIL;

struct riscv_program program;
riscv_program_init(&program, target);
if (riscv_program_insert(&program, csrr(S1, CSR_VTYPE)) != ERROR_OK)
return ERROR_FAIL;
if (riscv_program_insert(&program, vsetvl(ZERO, S0, S1)) != ERROR_OK)
return ERROR_FAIL;

return riscv_program_exec(&program, target);
}

static int csr_write_progbuf(struct target *target, enum gdb_regno number,
riscv_reg_t value)
{
assert(target->state == TARGET_HALTED);
assert(number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095);

if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;
if (register_write_abstract(target, GDB_REGNO_S0, value) != ERROR_OK)
return ERROR_FAIL;

struct riscv_program program;
riscv_program_init(&program, target);
if (riscv_program_csrw(&program, S0, number) != ERROR_OK)
return ERROR_FAIL;

return riscv_program_exec(&program, target);
}

/**
* This function writes a register by writing a program to program buffer and
* executing it.
*/
static int register_write_progbuf(struct target *target, enum gdb_regno number,
riscv_reg_t value)
{
assert(target->state == TARGET_HALTED);

if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31)
return fpr_write_progbuf(target, number, value);
else if (number == GDB_REGNO_VTYPE)
return vtype_write_progbuf(target, value);
else if (number == GDB_REGNO_VL)
return vl_write_progbuf(target, value);
else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095)
return csr_write_progbuf(target, number, value);

LOG_TARGET_ERROR(target, "Unexpected write to %s via program buffer.",
gdb_regno_name(number));
return ERROR_FAIL;
}

/**
* Immediately write the new value to the requested register. This mechanism
* bypasses any caches.
Expand Down

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