target/riscv: Don't write to zero.

During a previous patch, the ignoring of writes to register zero was deleted. This patch restores it to the original. Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c Signed-off-by: Marek Vrbka <[email protected]>
riscv-collab · Aug 21, 2023 · c52ffb9 · c52ffb9
1 parent 5cb60e3
commit c52ffb9
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
@@ -4718,6 +4718,10 @@ unsigned int riscv_count_harts(struct target *target)
  */
 static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write)
 {
+	/* Writes to register zero are rare and should always result in 0 */
+	if (regno == GDB_REGNO_ZERO)
+		return false;
+
 	/* GPRs, FPRs, vector registers are just normal data stores. */
 	if (regno <= GDB_REGNO_XPR31 ||
 			(regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||