Merge pull request #906 from MarekVCodasip/zero-no-cache

target/riscv: Don't write to zero.
riscv-collab · Aug 30, 2023 · 699eeca · 699eeca
2 parents 5efea16 + 0b914fe
commit 699eeca
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
@@ -4753,6 +4753,9 @@ unsigned int riscv_count_harts(struct target *target)
  */
 static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write)
 {
+	if (regno == GDB_REGNO_ZERO)
+		return !is_write;
+
 	/* GPRs, FPRs, vector registers are just normal data stores. */
 	if (regno <= GDB_REGNO_XPR31 ||
 			(regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||