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Bump riscv-gnu-toolchain spike submodule to latest master commit d1efcdf
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Submodule spike
updated
32 files
+1 −1 | .github/workflows/continuous-integration.yml | |
+3 −3 | Makefile.in | |
+42 −8 | arch_test_target/spike/model_test.h | |
+4 −3 | ci-tests/testlib.c | |
+28 −20 | disasm/disasm.cc | |
+1 −0 | disasm/disasm.mk.in | |
+7 −6 | disasm/isa_parser.cc | |
+2 −0 | fdt/fdt.mk.in | |
+1 −0 | fesvr/elfloader.cc | |
+120 −6 | riscv/csrs.cc | |
+59 −4 | riscv/csrs.h | |
+42 −9 | riscv/debug_module.cc | |
+6 −0 | riscv/debug_module.h | |
+6 −1 | riscv/decode_macros.h | |
+14 −5 | riscv/devices.h | |
+1 −1 | riscv/dts.cc | |
+1 −1 | riscv/dts.h | |
+78 −25 | riscv/encoding.h | |
+3 −1 | riscv/execute.cc | |
+3 −3 | riscv/insns/cbo_inval.h | |
+6 −6 | riscv/isa_parser.h | |
+5 −5 | riscv/mmu.cc | |
+13 −5 | riscv/mmu.h | |
+69 −6 | riscv/processor.cc | |
+2 −0 | riscv/processor.h | |
+0 −1 | riscv/riscv.mk.in | |
+9 −6 | riscv/sim.cc | |
+3 −2 | riscv/sim.h | |
+14 −5 | riscv/triggers.cc | |
+4 −2 | riscv/triggers.h | |
+5 −4 | spike_main/spike.cc | |
+4 −0 | spike_main/spike_main.mk.in |