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@TommyMurphyTM1234 @cmuellner
TommyMurphyTM1234 authored and cmuellner committed Oct 27, 2024
1 parent 7aa6d5e commit bb8990c
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Showing 2 changed files with 2 additions and 2 deletions.
2 changes: 1 addition & 1 deletion pk
Submodule pk updated 18 files
+4 −1 README.md
+2,102 −1,263 configure
+58 −0 machine/emulation.c
+1 −0 machine/emulation.h
+3,209 −12,732 machine/encoding.h
+1 −0 machine/machine.mk.in
+20 −17 machine/mentry.S
+8 −3 machine/minit.c
+24 −3 machine/misaligned_ldst.c
+140 −0 machine/misaligned_vec_ldst.c
+1 −0 machine/mtrap.h
+13 −8 pk/elf.c
+19 −0 pk/handlers.c
+5 −9 pk/mmap.c
+31 −1 pk/pk.c
+138 −0 pk/syscall.c
+2 −0 pk/syscall.h
+4 −1 scripts/config.sub
2 changes: 1 addition & 1 deletion spike
Submodule spike updated 73 files
+9 −0 Makefile.in
+16 −2 README.md
+1 −1 ci-tests/build-spike
+5 −2 ci-tests/test-spike
+0 −0 ci-tests/testlib.cc
+0 −6 config.h.in
+0 −33 configure
+1 −1 configure.ac
+50 −21 disasm/disasm.cc
+38 −10 disasm/isa_parser.cc
+2 −2 fdt/libfdt.h
+6 −12 fesvr/byteorder.h
+1 −0 fesvr/elfloader.h
+1 −1 fesvr/htif_pthread.h
+5 −2 riscv/cfg.cc
+383 −0 riscv/csr_init.cc
+103 −25 riscv/csrs.cc
+18 −5 riscv/csrs.h
+2 −2 riscv/debug_module.cc
+12 −8 riscv/decode_macros.h
+106 −50 riscv/dts.cc
+5 −6 riscv/dts.h
+17 −2 riscv/encoding.h
+5 −0 riscv/entropy_source.h
+33 −10 riscv/execute.cc
+23 −24 riscv/insn_template.cc
+1 −1 riscv/insns/c_ld.h
+1 −1 riscv/insns/c_ldsp.h
+1 −1 riscv/insns/c_sd.h
+1 −1 riscv/insns/c_sdsp.h
+9 −1 riscv/insns/dret.h
+1 −2 riscv/insns/fcvtmod_w_d.h
+1 −0 riscv/insns/jal.h
+1 −0 riscv/insns/jalr.h
+2 −1 riscv/insns/mret.h
+9 −0 riscv/insns/sret.h
+5 −4 riscv/insns/vcompress_vm.h
+3 −3 riscv/insns/vnclip_wi.h
+3 −3 riscv/insns/vnclip_wv.h
+3 −3 riscv/insns/vnclip_wx.h
+3 −3 riscv/insns/vnclipu_wi.h
+3 −3 riscv/insns/vnclipu_wv.h
+3 −3 riscv/insns/vnclipu_wx.h
+4 −4 riscv/insns/vsmul_vv.h
+4 −4 riscv/insns/vsmul_vx.h
+1 −1 riscv/insns/vssra_vi.h
+1 −1 riscv/insns/vssra_vv.h
+1 −1 riscv/insns/vssra_vx.h
+1 −1 riscv/insns/vssrl_vi.h
+1 −1 riscv/insns/vssrl_vv.h
+1 −1 riscv/insns/vssrl_vx.h
+8 −11 riscv/interactive.cc
+5 −1 riscv/isa_parser.h
+1 −1 riscv/log_file.h
+88 −32 riscv/mmu.cc
+22 −30 riscv/mmu.h
+2 −0 riscv/platform.h
+1 −1 riscv/plic.cc
+46 −424 riscv/processor.cc
+15 −8 riscv/processor.h
+0 −12 riscv/riscv.ac
+1 −0 riscv/riscv.mk.in
+60 −45 riscv/sim.cc
+0 −1 riscv/sim.h
+70 −31 riscv/triggers.cc
+2 −2 riscv/triggers.h
+10 −10 riscv/v_ext_macros.h
+8 −8 riscv/vector_unit.cc
+39 −7 softfloat/f64_to_bf16.c
+0 −5 softfloat/softfloat.mk.in
+1 −1 spike_dasm/spike-dasm.cc
+2 −2 spike_main/spike-log-parser.cc
+31 −42 spike_main/spike.cc

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