Add missing legacy file for xilinx port of tech_cells (#10)

pulp-platform · Feb 3, 2021 · fea9134 · fea9134
1 parent 63da150
commit fea9134
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -14,6 +14,7 @@ sources:
   - target: all(fpga, xilinx)
     files:
       - src/deprecated/cluster_clk_cells_xilinx.sv
+      - src/deprecated/pulp_clk_cells_xilinx.sv
       - src/fpga/tc_clk_xilinx.sv
       - src/fpga/tc_sram_xilinx.sv