Add optional parameter to tc_clk_gating to flag functional gates (#22)

* Add optional parameter to tc_clk_gating to flag functional gates

* Update changelog

CHANGELOG.md

@@ -5,6 +5,9 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
 ## Unreleased
+### Changed
+- Added optional `IS_FUNCTIONAL` flag to `tc_clk_gating` cell to optionally mark them as *not required for functionality*.
+
 ## 0.2.4 - 2021-02-04
 - Add `deprecated/pulp_clk_cells_xilinx.sv` to `Bender.yml`
 

src/rtl/tc_clk.sv

@@ -28,7 +28,14 @@ module tc_clk_buffer (
 endmodule
 
 // Description: Behavioral model of an integrated clock-gating cell (ICG)
-module tc_clk_gating (
+module tc_clk_gating #(
+  /// This paramaeter is a hint for tool/technology specific mappings of this
+  /// tech_cell. It indicates wether this particular clk gate instance is
+  /// required for functional correctness or just instantiated for power
+  /// savings. If IS_FUNCTIONAL == 0, technology specific mappings might
+  /// replace this cell with a feedthrough connection without any gating.
+  parameter bit IS_FUNCTIONAL = 1'b1
+)(
    input  logic clk_i,
    input  logic en_i,
    input  logic test_en_i,