Release 0.1.6 partial (#3)

* Clean-up * Deprecate pulp* and cluster* cells, merge similar cells into same file * Add power cells * CONTRIBUTING.md: Remove text and link to central repo * Update CHANGELOG.md
pulp-platform · Nov 18, 2019 · 04b7b27 · 04b7b27
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diff --git a/Bender.yml b/Bender.yml
@@ -5,39 +5,21 @@ package:
 sources:
   - target: all(fpga, xilinx)
     files:
-      - src/cluster_clock_gating_xilinx.sv
-      - src/pulp_clock_gating_xilinx.sv
-      - src/pulp_clock_mux2_xilinx.sv
+      - src/deprecated/cluster_clk_cells_xilinx.sv
+      - src/fpga/tc_clk_xilinx.sv
 
   - target: not(all(fpga, xilinx))
     files:
-      - src/cluster_clock_gating.sv
-      - src/pulp_clock_gating.sv
-      - src/pulp_clock_mux2.sv
+      - src/deprecated/cluster_clk_cells.sv
+      - src/deprecated/pulp_clk_cells.sv
+      - src/rtl/tc_clk.sv
 
   - target: not(synthesis)
     files:
-      - src/cluster_clock_and2.sv
-      - src/cluster_clock_buffer.sv
-      - src/cluster_clock_inverter.sv
-      - src/cluster_clock_mux2.sv
-      - src/cluster_clock_xor2.sv
-      - src/cluster_level_shifter_in.sv
-      - src/cluster_level_shifter_in_clamp.sv
-      - src/cluster_level_shifter_inout.sv
-      - src/cluster_level_shifter_out.sv
-      - src/cluster_level_shifter_out_clamp.sv
-      - src/generic_memory.sv
-      - src/generic_rom.sv
-      - src/pad_functional.sv
-      - src/pulp_buffer.sv
-      - src/pulp_clock_and2.sv
-      - src/pulp_clock_buffer.sv
-      - src/pulp_clock_gating_async.sv
-      - src/pulp_clock_inverter.sv
-      - src/pulp_clock_xor2.sv
-      - src/pulp_level_shifter_in.sv
-      - src/pulp_level_shifter_in_clamp.sv
-      - src/pulp_level_shifter_out.sv
-      - src/pulp_level_shifter_out_clamp.sv
-      - src/pulp_power_gating.sv
+      - src/deprecated/cluster_pwr_cells.sv
+      - src/deprecated/generic_memory.sv
+      - src/deprecated/generic_rom.sv
+      - src/deprecated/pad_functional.sv
+      - src/deprecated/pulp_buffer.sv
+      - src/deprecated/pulp_pwr_cells.sv
+      - src/tc_pwr.sv
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -6,6 +6,15 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## Unreleased
 
+## 0.1.6 - 2019-11-18
+### Added
+- Add Readme
+- Add Contribution Guide
+
+### Changed
+- Move modules of similar topic to a single file. This makes it easier to add new modules.
+- Move separation between `cluster` and `pulp` to `deprecated` folder. There should be a single solution to a tech-cell.
+
 ## 0.1.1 - 2018-09-12
 ### Changed
 - Polish release
@@ -14,4 +23,4 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## 0.1.0 - 2018-09-12
 ### Added
-- Initial commit.
+- Initial commit.
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
@@ -0,0 +1,3 @@
+# Contributing
+
+See [our style and contribution guidelines](https://github.com/pulp-platform/style-guidelines).
diff --git a/README.md b/README.md
@@ -0,0 +1,54 @@
+# Generic Technology Cells (API to Cell Library)
+
+Maintainer: Florian Zaruba <[email protected]>
+
+This repository contains technology related cells like SRAMs, clock-gating cells, power management cells. The description here are:
+
+- **Behavioral**: Meant for RTL simulation only.
+- **FPGA**: Meant for FPGA implementation. Currently we only support Xilinx FPGAs. But we are happy to accept patches for Altera or other devices.
+
+It is the purpose of your technology specific file to include the cells with correct drive strength. We do not make the assumption in the front-end anymore.
+
+> As this layer needs to be re-implemented for every new technology keep it thin!
+
+## Cell Contents
+
+If you want to get started in your own technology (either an unsupported FPGA or an ASIC technology) please provide implementations for the cells in this repository.
+
+### Clock Cells
+
+Clock cells usually are care-fully designed cells which do not exhibit any glitches. Therefore they need to be manually instantiated in ASIC designs. All clock cells can be found in `tc_clk.sv`.
+
+|        Name       |         Description          | Status |       Xilinx       |
+|-------------------|------------------------------|--------|--------------------|
+| `tc_clk_and2`     | Clock and gate               | active | :white_check_mark: |
+| `tc_clk_buffer`   | Clock buffer                 | active | :white_check_mark: |
+| `tc_clk_gating`   | Integrated clock gating cell | active | :white_check_mark: |
+| `tc_clk_inverter` | Clock inverter               | active | :white_check_mark: |
+| `tc_clk_mux2`     | Clock Mux with two inputs    | active | :white_check_mark: |
+| `tc_clk_xor2`     | Clock Xor                    | active | :white_check_mark: |
+| `tc_clk_delay`    | Programmable clock-delay     | active |                    |
+
+### Memory
+
+|    Name   |                       Description                        | Status |       Xilinx       |
+|-----------|----------------------------------------------------------|--------|--------------------|
+| `sp_sram` | Single-ported SRAM with bit-error injection capabilities | active | :white_check_mark: |
+| `dp_sram` | Dual-ported SRAM with bit-error injection capabilities   | active | :white_check_mark: |
+| `mp_sram` | Multi-ported SRAM with bit-error injection capabilities  | active |                    |
+
+### Power Cells
+
+Power cells are mostly used for advanced power gating features and not used in any of our open-source IPs. However, feel-free to re-use them. All clock cells can be found in `tc_pwr.sv`.
+
+|                 Name                |             Description              | Status |
+|-------------------------------------|--------------------------------------|--------|
+| `tc_pwr_level_shifter_in`           | Level Shifter                        | active |
+| `tc_pwr_level_shifter_in_clamp_lo`  | Level Shifter w/ clamp to `1'b0`     | active |
+| `tc_pwr_level_shifter_in_clamp_hi`  | Level Shifter w/ clamp to `1'b1`     | active |
+| `tc_pwr_level_shifter_out`          | Level Shifter                        | active |
+| `tc_pwr_level_shifter_out_clamp_lo` | Level Shifter w/ clamp to `1'b0`     | active |
+| `tc_pwr_level_shifter_out_clamp_hi` | Level Shifter w/ clamp to `1'b1`     | active |
+| `tc_pwr_power_gating`               | Power Gate with ctrl and status pins | active |
+| `tc_pwr_isolation_lo`               | Isolation Cell w/ isolate to `1'b0`  | active |
+| `tc_pwr_isolation_hi`               | Isolation Cell w/ isolate to `1'b1`  | active |
diff --git a/src/cluster_clock_and2.sv b/src/cluster_clock_and2.sv
diff --git a/src/cluster_clock_buffer.sv b/src/cluster_clock_buffer.sv
diff --git a/src/cluster_clock_gating.sv b/src/cluster_clock_gating.sv
diff --git a/src/cluster_clock_gating_xilinx.sv b/src/cluster_clock_gating_xilinx.sv
diff --git a/src/cluster_clock_inverter.sv b/src/cluster_clock_inverter.sv
diff --git a/src/cluster_clock_mux2.sv b/src/cluster_clock_mux2.sv
diff --git a/src/cluster_clock_xor2.sv b/src/cluster_clock_xor2.sv
diff --git a/src/cluster_level_shifter_in.sv b/src/cluster_level_shifter_in.sv
diff --git a/src/cluster_level_shifter_in_clamp.sv b/src/cluster_level_shifter_in_clamp.sv
diff --git a/src/cluster_level_shifter_inout.sv b/src/cluster_level_shifter_inout.sv
diff --git a/src/cluster_level_shifter_out.sv b/src/cluster_level_shifter_out.sv
diff --git a/src/cluster_level_shifter_out_clamp.sv b/src/cluster_level_shifter_out_clamp.sv